LIN-CTRL

LIN Bus Master/Slave Controller

The LIN-CTRL core is partitioned into modules as shown in the block diagram.

Host Controller Interface
This interface is responsible for handling the communication with the host controller of the system.

Register Block
The Register Block provides control registers and status registers to control the LIN message transfer. Access to the registers is possible via the host controller interface.

Data Buffer
The 8-byte Data Buffer stores the data that has to be sent with the current LIN frame or the data that has been received with the last LIN frame. Access to the Data Buffer is possible via the host controller interface.

Control FSM
The finite control state machine is responsible for the behavior of the core depending on host controller commands and bus activity. It generates and processes the LIN frame fields according to the LIN protocol. 

Bit Stream Processor
This module converts the data stream from parallel to serial (from transmit buffer to bus) and from serial to parallel (from bus to receive buffer).

Bit Timing Logic
The Bit Timing Logic is responsible for synchronizing the received data stream from the bus with the internal bit time clock.

Core Modifications

The LIN controller core can be modified to include an acceptance filter. With that, a simple LIN slave that transmits response frames for only one identifier could be realized without the assistance of a host controller. Please contact CAST, Inc. directly for any required modifications.

Verification

The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in several shipping customer products, and is proven in both ASIC and FPGA technologies.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms. It ships with everything required for successful implementation, including:

• Verilog RTL source code, or targeted FPGA netlist
• Testbenches for behavioral, and post-synthesis verification • Simulation and Synthesis scripts
• Low-Level Hardware Abstraction Layer (HAL)
• Optional MISRA C non-OS, bare-metal driver with advanced software examples
• User Documentation and IP-XACT register descriptions.

The optional safety-enhanced package further includes the Safety Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA) and the ASIL-D Ready certificate, issued by SGS-TÜV Saar GmbH.

LIN-CTRL reference designs have been evaluated in a variety of technologies. The following are sample ASIC results.

¹ Minimum clock frequency for the LIN controller is 8 MHz

The LIN-CTRL core can be mapped to any Altera FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following are sample implementation data for the core assuming all I/Os are routed off-chip.

¹ Minimum clock frequency for the LIN controller is 8 MHz

The LIN-CTRL core can be mapped to any AMD FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following are sample implementation data for the core assuming all I/Os are routed off-chip.

¹ Minimum clock frequency for the LIN controller is 8 MHz

The LIN-CTRL core can be mapped to any Lattice FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following are sample implementation data for the core assuming all I/Os are routed off-chip.

¹ Minimum clock frequency for the LIN controller is 8 MHz

The LIN-CTRL core can be mapped to any Microsemi FPGA device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following are sample implementation data for the core assuming all I/Os are routed off-chip.

¹ Minimum clock frequency for the LIN controller is 8 MHz