JPEG-D-S
Baseline JPEG Decoder

This JPEG decompression IP core supports the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It implements a high-performance, ASIC or FPGA, hardware JPEG decoder that is very small in silicon area.  

The JPEG-D-S Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8-bit color samples and up to four color components, in all widely-used color subsampling formats.  

The decoder processes one color sample per clock cycle, enabling it to process multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG decoders available, it requires just 65,000 equivalent gates when mapped on an ASIC technology.  

Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. 

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.  

Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.  

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.

    The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products and is proven in both ASIC and FPGA technologies. 

    Support 

    The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

    Deliverables 

    The core is available in FPGA netlist form and includes everything required for successful implementation. Its deliverable package includes: 

    • Netlist 
    • Sophisticated self-checking Testbench  
    • Software (C++) Bit-Accurate Model  
    • Sample simulation and synthesis scripts 
    • Comprehensive user documentation 

    The JPEG-D-S Encoder core synthesizes to approximately 65K gates and requires 20k bits of memory. 

    The JPEG-D-S can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. 

      720p60 
    4:2:0
    1080p30 
    4:2:2
    1080p60 
    4:2:0
    Logic Resources MULTs/DSPs Memory Bits

    Max10

     

     

     

    9,800 LEs

    10

    31,552

    CycloneV

     

     

     

    4,000 ALMs

    5

    31,706

    Arria10

     

     

     

    4,000 ALMs

    5

    31,706

    StratixV

     

     

     

    4,000 ALMs

    5

    31,706


    Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology. 

    The JPEG-D-S can be mapped to any Xilinx Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core.  

     

    1080p30
    4:4:4

    1080p60
    4:2:0

    1080p60
    4:2:2

    LUTs DSPs BRAMs

    Artix-7 (-2)

          6,800 5 2 RAMB16

    Kintex7 (-2)

          6,100 5 2 RAMB16

    Kintex7-US (-1)

          5,900 5 2 RAMB16


    Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology. 

    Related Content

    Features List

    Area-efficient, high-performance Baseline JPEG decoder for ASIC and FPGA 

    Standards Support 

    • ISO/IEC 10918-1 Standard Baseline Decoder  
    • Single-frame JPEG images and Motion JPEG payloads 
    • Up to four color components 
    • 8-bit color samples 
    • All widely used color subsampling formats, and any image size up to 64k x 64k  
    • All scan configurations and all JPEG formats  
    • All marker segments expect DNL 
    • Up to four Huffman Tables  
    • Up to four 8-nit or 16-bit Quantization tables  

    Interfaces 

    • AXI Streaming I/O data interfaces 
    • APB Control/Status interface 
    • Optional AHB wrapper with DMA capabilities 

    Performance and Size 

    • One decoded sample per clock cycle 
    • Small silicon footprint (~65k Gates) 

    Ease of Integration 

    • Requires no programming or control from host  
    • Reports image format 
    • Detects and reports marker syntax errors 
    • Delivered with bit-accurate software model  
    • Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer 

    Format 

    • Available as a netlist for ASICs or FPGAs 

    Resources

    See the JPEG entry at Wikipedia.

    See the Motion JPEG entry at Wikipedia.

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