Silicon IP Cores
ASCON-F
ASCON Authenticated Encryption & Hashing Engine
The ASCON-F IP core is a compact, high-throughput hardware engine implementing the lightweight authenticated encryption with associated data (AEAD) and hashing algorithms described in the Ascon v1.2 specification.
A single instance of the ASCON-F IP core can encrypt or decrypt data using the Ascon-128 and Ascon-128a functions or perform Cryptographic hashing Hash per the Ascon-Hash and Ascon-Hasha functions. The mode of operation (encryption or decryption, and Ascon function), as well as the encryption key and nonce values, are run-time programmable and can be changed per block of input data. The core uses simple input and output interfaces, that can be optionally bridged to AXI4-Stream, or to AXI4 Memory Mapped master or slave ports using bridges separately available from CAST.
The core synthesizes to approximately 11k gates and is able to run at frequencies exceeding 2 GHz in modern ASIC technologies. Ignoring overheads related to input padding and core initialization, the throughput ranges from 5.3 to 16 bits/cycle depending on the mode and function, which at 2 GHz translates to 10.6 to 32 Gbps. The processing throughput can be further scaled by instantiating the core multiple times.
The core is designed for ease of use and integration and adheres to industry-best coding and verification practices. Technology mapping and timing closure are trouble-free, as the core contains no multi-cycle or false paths and uses only rising-edge-triggered D-type flip-flops, no tri-states, no SRAMs, and a single-clock/reset domain.
About ASCON
The ASCON family of algorithms was developed by Graz University of Technology, Infineon Technologies, Lamarr Security Research, and Radboud University and was selected in February 2023 by the US National Institute of Standards and Technology (NIST) as the new standard for lightweight cryptography. Learn more online at NIST, Wikipedia, and the Ascon website by Graz University of Technology.
Applications
Implementing the Ascon family of lightweight authenticated ciphers and hash functions, the core can be used to protect edge IoT devices, secure communications or video surveillance systems, and encrypt data storage.
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Deliverables
The core is available in RTL source or as a targeted FPGA netlist. It is delivered with everything required for a successful implementation, including a sophisticated, self-checking HDL Testbench, a behavioral C Model & test vector generator, and comprehensive documentation.
The ASCON-F IP core can be mapped to any ASIC technology or FPGA device. The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip.
ASIC Technology |
Logic |
Memory |
Freq |
---|---|---|---|
TSMC 7nm |
10,544 |
0 |
2,300 |
TSMC 16nm |
10,584 |
0 |
2,150 |
TSMC 28nm HPC |
11,283 |
0 |
1,900 |
The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.
The ASCON-F IP core can be mapped to any Altera FPGA device. The following are sample implementation results reported from Quartus, with all core I/Os assumed to be routed on-chip.
Family/Device |
Logic |
Memory bits |
Freq. |
---|---|---|---|
Agilex |
1,295 ALMs |
0 |
700 |
Arria 10 GX |
1,225 ALMs |
0 |
525 |
Cyclone V GX |
1,207 ALMs |
0 |
250 |
Max10 (-7) |
2,058 LEs |
0 |
175 |
Stratix V |
1,173 ALMs |
0 |
500 |
The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.
The ASCON-F IP core can be mapped to any AMD FPGA device. The following are sample implementation results as reported by Vivado, with all core I/Os assumed to be routed on-chip.
Family/Device |
Logic |
Memory |
Freq. |
---|---|---|---|
KINTEX 7 |
1,202 |
0 |
475 |
KINTEX UltraScale |
1,223 |
0 |
700 |
KINTEX UltraScale+ |
1,211 |
0 |
900 |
Versal Premium |
1,481 |
0 |
625 |
The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.
Engineered by Ocean Logic.
Features List
- Authenticated Encryption and Hashing per NIST submitted specification Ascon v1.2
- Ascon-128 and Ascon-128a authenticated encryption/decryption
- Ascon-Hash & Ascon-Hasha hash functions
- Ascon-Xof, Ascon-Xofa, and Ascon-80pq on request
- Run-time selectable operation mode, encryption key and nonce
Compact and Fast
- Approximately 11,000 eq. gates
- More than 2GHz on modern ASIC technologies
- Throughput without any initialization and padding overhead:
- Ascon-128: 10.6 bits/cycle
- Ascon-128a: 16 bits/cycle
- Ascon-Hash: 5.3 bits/cycle
- Ascon-Hasha: 8 bits/cycle
Easy to integrate & implement.
- Fully synchronous, uses only the rising clock-edge, single-clock domain, no false or multicycle timing paths, scan-ready, LINT-clean
- Simple input and output interface, optionally bridged to AMBA® interfaces or integrated with a DMA engine.
- Available VHDL or Verilog source code format, or as a targeted FPGA
- Soft, technology-agnostic IP core directly synthesizes to any FPGA or ASIC technology
Resources
Ascon — Lightweight Authenticated Encryption & Hashing
Introductory website, Univ. of Graz
Ascon v1.2 Submission to NIST
Dobraunig, C., Eichlseder, M., Mendel, F. et al.
ASCON v1.2: Lightweight Authenticated Encryption and Hashing
Dobraunig, C., Eichlseder, M., Mendel, F. et al. , Journal of Crytography