JPEG-DX-F

Ultra-Fast Baseline and Extended JPEG Decoder

This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates.  

The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.  

Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provide an extremely cost-effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.  

Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. 

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.  

Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.  

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model. 

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies. 

Support 

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

Deliverables 

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes: 

• Verilog RTL source code 
• Sophisticated self-checking Testbench  
• Software (C++) Bit-Accurate Model 
• Sample simulation and synthesis scripts 
• Comprehensive user documentation

The silicon resources requirements for the JPEG-DX-F decoder core depend on its configuration. A two samples per cycle configuration synthesizes to approximately 110K gates and requires 50k-bits of memory. 

The JPEG-DX-F can be mapped to any Altera FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the core configured to process 2 samples per cycle (JPEG-DX-F/2) and under its default configuration.  

Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology. 

The JPEG-DX-F can be mapped to any AMD Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data the core configured to process 2 samples per cycle (JPEG-DX-F/2) and under its default configuration.  

Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology. 

The JPEG-DX-F can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data the core configured to process 2 samples per cycle (JPEG-DX-F/2) and under its default configuration. 

Note that the implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology. 

The JPEG-DX-F core can be mapped to any Microchip Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the core configured to process 2 samples per cycle (JPEG-DX-F/2) and under its default configuration.

Note that the list of video formats is not exhaustive and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology.