Silicon IP Cores
The H264-E-CFS IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It Implements an energy-efficient hardware architecture that is optimized for ultra-low-latency video streaming at low bit rates. No DRAM is required due to the patented Compressed Reference Frame Store (CFS) technology.
The H264-E-CFS encoder requires less than half the silicon area of most hardware encoders—approximately 180K gates—allowing for very cost-effective ASIC or FPGA implementations. Its small silicon footprint, low external memory bandwidth requirements, and zero software overhead enable H.264 coding with an extremely low energy cost. The encoder is able to process beyond Full-HD video when mapped on modern ASIC technologies, and HDTV when mapped on FPGAs.
Despite being small, the H264-E-CFS produces high quality video, especially at low bit rates, and is suitable for systems with low-latency requirements. It uses constant quantization to output video streams of Variable Bit-Rate (VBR), or automatically regulates quantization multiple times within a frame to output Constant Bit-Rate (CBR) streams. In CBR mode it responds rapidly to temporal or spatial changes in the video content. This can be combined with an artifacts-free Intra-Refresh coding implementation to effectively eliminate bit-rate peaks, while preserving the periodic intra-coded references. As a result, the stream buffers can be smaller than those typically required, and the end-to-end latency can be brought down to frame or sub-frame levels. Video quality at low bit rates is preserved, as the encoder intelligently uses block skipping and quantization coefficient thresholding to reduce the bit rate with minimal quality loss, and uses the in-loop deblocking filter to eliminate the blocking artifact.
The core was designed for ease of use and integration. Once initially programmed, it operates without any assistance from the host processor. The core is optionally delivered with a raster-to-block converter, and wrappers for AMBA® AHB, AXI, or AXI-Streaming buses are available.
Customers can further decrease their time to market by using CAST’s integration services to receive complete video encoding subsystems. These integrate the encoder core with video and networking interface controllers, networking stacks, or other CAST or third-party IP cores.
The H264-E-CFS IP core is designed using with industry best practices and is production proven. Its deliverables include a complete verification environment and a bit-accurate software model.
The core stores reference images used during motion estimation in a compressed frame store (CFS) format using patented technology. Depending on the quality required in the H.264 encoded bitstream, compression in the CFS can be as high as 10–15:1. No reconstruction error or drift is present when the output H.264 bitstream is decoded with a standard decoder.
The CFS brings the following power advantages:
The H264-E-CFS synthesizes to approximately 180K gates and requires 217K bits of internal memory. It can process UHD/4K at 30fps on modern ASIC technologies.
The core is available in source-code VHDL or as a targeted netlist, and its deliverables include everything required for successful implementation:
Potential customers can readily evaluate the video encoder’s compression efficiency can be evaluated by using:
Engineered by Ocean Logic.