Silicon IP Cores
The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is based on the Intel® 8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control.
The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80C51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation.
The controller’s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud rate is programmable and limited only by the link drivers and the core’s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock.
The HSDLC is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements triple-modular redundancy (TMR) to provide full immunity to single-bit upsets and errors and complies to Design Assurance, Level A (DAL-A) of the DO-254 standard.
The HSDLC controller core is designed for reuse and is rigorously verified and scan-ready. Although designed to manage serial links, the core contains no latches or tri-states, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.
The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in several shipping customer products, and is proven in both ASIC and FPGA technologies.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.
HSDLC core reference designs have been evaluated in a variety of technologies. The following are sample results, for the core configured with Tx and Rx FIFOs. FIFOs are 3 bytes each and implemented with flip-flops. Please contact CAST to get characterization data for your target configuration and technology.
| ASIC Technology | Area (eq. NAND2 gates) |
Max. Freq. (MHz) |
|---|---|---|
| TSMC 65nm LP | 7,575 | 400 |
| TSMC 40nm G | 5,594 | 1,200 |
| TSMC 28nm HPM | 4.588 | 1,800 |
The HSDLC can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.
| Family / Device |
Logic | Memory Bits |
Frequency (MHz) |
|---|---|---|---|
|
Cyclone-V |
412 ALMs | 0 | 162 |
|
Arria-V 5AGXBB3D4F35C4 |
414 ALMs | 0 | 202 |
|
Arria10 10AS057K2F35I2LG |
420 ALMs | 0 | 327 |
|
Max10 10M50DAF484C6GES |
836 LEs | 0 | 136 |
The HSDLC can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.
| Family Device |
LUTs | RAMBs/DPSs | Performance (MHz) |
|---|---|---|---|
|
Artix UltraScale+ XCAU25-1 |
767 | 0/0 | 500 |
|
Kintex UltraScale+ XCKU11P-1 |
765 | 0/0 | 500 |
|
Zynq Ultrascale+ XCZU4EG-1 |
770 | 0/0 | 520 |
|
Zynq 7000 7Z045-1 |
714 | 0/0 | 230 |
The HSDLC can be mapped to any Microchip FPGA (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data for the core implemented with an 8-entires FIFO. Please contact CAST to get characterization data for your target configuration and device.
| Family / Device |
Logic Resources |
Memory Resources |
Freq. (MHz) |
|---|---|---|---|
| Igloo2 M2GL150-STD |
1,036 4LUTs | 2 RAM64x18 | 75 |
| PolarFire MPF500T-STD |
1,031 4LUTs | 2 uSRAM | 100 |
| RTG4 RT4G150-STD |
1,036 4LUTs | 2 RAM64x18 | 75 |
| SmartFusion2 M2S150-STD |
1,036 4LUTs | 2 RAM64x18 | 75 |