H16550S

UART with FIFOs and Synchronous CPU Interface

The H16550S includes the following six major blocks.  All the core’s inputs and outputs are fully synchronous to the rising edge of the CLK input. 

Interface (RWCONTROL) 

Handles communication with the processor (or parallel) side of the system. Manages all writing and reading of internal registers. 

Registers (UART_REG) 

Holds all of the device’s internal registers. Some information comes from the other blocks, but it is all gathered in the Registers block and made available to all blocks. 

RXBlock 

Handles the receiving of the incoming serial word. It is programmable to recognize data widths such as 5, 6, 7 or 8 bits, various parity settings, and different stop bits of 1, 1½ and 2 bits. It checks for errors in the input data stream, and if the incoming word has no problems it is placed either in the Receiver Holding register or in the Receiver FIFO depending on the mode programmed. 

Interrupt Control 

Sends an interrupt signal back to the processor depending on the state of the FIFO and its received and transmitted data. Various levels of interrupt can be read from the Interrupt Identification register. Interrupts are sent in the condition of empty transmission or receiving buffers (or FIFOs), an error in the receiving of a character, or other conditions requiring the attention of the processor. 

Baud Rate Generator 

Takes the input clock, CLK, and divides it by a programmed value (from 1 to 216 – 1). This divided clock is then divided by 16 to create the transmission clock called the Baudout clock.  

TXBlock 

Handles the transmission of data written to the Transmission Holding register (or transmit FIFO). It adds required start, parity and stop bits to the data being transmitted so that the receiving device can do the proper error handling and receiving. 

The H16550S core is modeled after the Texas Instruments 16550, with the following differences: 

• No provision is made for a crystal. The CLK input is designed to accept a standard digital input. 
• The RCLK input in the Asynchronous version is replaced by CLK with rclk_enb which has the same frequency as BAUDOUTn.     The bi-directional Data Bus has been split into an input and an output component. In order to use the core with a bi-directional Data Bus, the DDIS signal can be used as the controlling signal for the tri-state drivers. 
• RD2, WR2, CS1 and CS2 have been eliminated. A single signal takes their place. These are RD, WR and CS. 
• The ADSN signal has been removed. The H16550S functions as if the ADSN signal is held low. The included wrapper can be used to add the ADSN functionality latching the address and data buses. 
• The main clock input CLK must be active from power-up. 
• The Baudrate Generator is reset to the 0001h value upon activation of the MR signal. Programming the BRG to 0000h is an illegal value. The minimum value for the BRG is 0001h. Until the BRG is programmed, no output is generated. 
• The Output Data Bus always shows the value of the last register read. 
   

The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in several shipping customer products, and is proven in both ASIC and FPGA technologies. 
 

Support 

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

Deliverables 

The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation. 

The H16550S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

The H16550S can be mapped in any Altera FPGA device, provided sufficient logic resources are available. It occupies approximately 600 LEs, and can be clocked at frequencies exceeding 250MHz in modern FPGA devices.

The H16550S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data with IOBs assuming all core I/Os are routed off-chip.  Different results can be obtained by optimizing slices for area or speed. Please contact CAST to get characterization data for your target configuration and technology.

The H16550S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

The H16550S can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.