TCPIP-1G/10G

1G/10G TCP/IP Hardware Stack

The TCPIP-1G/10G core is available in synthesizable Verilog RTL and FPGA netlist forms. Its deliverable package includes everything required for successful implementation:

• Comprehensive user documentation,
• A sample integration testbench, and optionally a UVM-based verification environment
• Sample synthesis and simulation scripts, and
• A software driver with an easy-to-use API

Sample designs integrating the TCPIP-1G/10G with third-party or CAST’s Ethernet MAC and/or memory controller IP cores are available upon request. Such integrated designs are readily available for devices from all the major FPGA vendors. Please contact CAST to learn more details.

Its high bandwidth, low latency, and autonomous operation make the TCPIP-1G/10G core suitable for a variety of systems, including data and web servers, NIC cards, network security, network storage, electronic trading, industrial systems, and automotive ethernet.

The TCPIP core receives and transmits TCP packet data and forwards other traffic from the Ethernet MAC to the application and vice versa. It also receives and transmits ARP requests and responses, and responds to ICMP echo reply messages. Optionally the core can also support the UDP and DHCP protocols.

The core consists of the following modules:

• The Ethernet module sends/receives Ethernet frames to/from an external Ethernet MAC, detects the frame type and multiplexes frames between the protocol stack subsystems.
• The VLAN Tx/Rx module receives Ethernet frames from an external Ethernet MAC, and when enabled detects and compares VLAN tag ; filters frames to the correct VLAN tag. In the transmission direction, the module receives Ethernet frames from the Ether-net Frame module and adds the VLAN Tag to the frames when enabled.
• The ARP module sends and receives ARP packets and handles the packets according to command in the packet. It provides the IP-to-MAC address translation services to the IPv4 layers in the protocol stacks.
• The IPv4 module processes the received frames and distributes decoded frames to the related protocol stack modules. Frames from the upper protocol layers are encapsulated into the IPv4 frames and passed to the Ethernet module.
• The TCP module provides the primary functionality of the TCPIP-1G/10G core, i.e. the TCP stack. The TCP stack is fully implemented in hardware. The transmit and receive buffers are located in an external memory accessed via the AXI bus. 
• The ICMP module supports the echo request response (ping).
• The UDP module is responsible for processing UDP packets for the DHCP module. The module can also provide user UDP channels to the user's design.
• The IGMP module adds the IGMP protocol stack needed for UDP multicast support. The module is optional and requires user UDP channels feature enabled.
• The DHCP module automatically requests and acquires an IP address from a DCHP server. The DHCP feature is optional and requires the UDP module.
•  The Control and Status Registers control the core functionality and report its status.

The TCPIP-1G/10G can be mapped in any Altera FPGA device, provided sufficient resources are available. The FPGA resources required for the implementation of the core depend on its configuration. The following table provides sample implementation data for a few out of the many possible configurations of the core.

Table 1. FPGA resources requirements for the TCPIP-1G/10G core with one UDP channel per direction, no OoO packet reordering, and clocked at 156 MHz on an Agilex device.

The above table does not list all configuration options. Please contact CAST to get characterization data for your configuration and target device.

The TCPIP-1G/10G can be mapped in any AMD FPGA device, provided sufficient resources are available. The FPGA resources required for the implementation of the core depend on its configuration. The following table provides sample implementation data for a few out of the many possible configurations of the core.

Table 1. FPGA resources requirements for the TCPIP-1G/10G core with one UDP channel per direction, no OoO packet reordering, and clocked at 156 MHz on an ARTIX™ Ultrasclale+ device

The above table does not list all configuration options. Please contact CAST to get characterization data for your configuration and target device.

The TCPIP-1G/10G can be mapped in any Lattice FPGA device, provided sufficient resources are available. The FPGA resources required for the implementation of the core depend on its configuration. The following table provides sample implementation data for a few out of the many possible configurations of the core.

Table 1. FPGA resources requirements for the TCPIP-1G/10G core with one UDP channel per direction, no OoO packet reordering, and clocked at 62.5 MHz on a CertusPro NX device.

The above table does not list all configuration options. Please contact CAST to get characterization data for your configuration and target device.

The TCPIP-1G/10G as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.