KEXP

AES Key Expander

The KEXP is a highly integrated implementation of the AES key expansion. The input key is expanded and it can be used during encryption on the fly, without the need to store the whole key in a buffer. 

During decryption, the expanded key needs to be fed backwards. This core can perform backward expansion on the fly without the need for an additional buffer. 

Rising the input on the GO port triggers the beginning of the expansion of the KEY input. 

The key size selection can be selected by the KSIZE input. Valid values for KSIZE are “00”, ”01” and “10” selecting 128, 192 or 256 bits respectively. The KSIZE inputs must not be changed while the data is processed. 

The core then raises the KEY_REQ signal requesting the key. It then starts to expand the key according to the AES algorithm 

During the expansion process, the expanded key data is available at the output KEY. 

The expanded data is output in the correct order for use with AES cores during encryption. 

At the end of the expansion operation, the signal KEY_LAST is raised. The core is immediately ready for another expansion operation and, in fact, the KEY_REQ signal is raised immediately after that. 

Backward Key Expansion 

During decryption, the expanded key must be fed to an AES core backwards. Backwards expansion works similarly to forward expansion and it is activated by raising the E_D input. Export Permits 

This core implements encryption functions and as such it is subject to export control regulations. Export to your country may or may not require a special export license. Please contact CAST to determine what applies in your specific case. 
 

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies. 
 

Support 

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

Deliverables 

The core is available in ASIC (RTL) or FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes 

•     HDL RTL source 
•     Sophisticated HDL Testbench (self-checking) 
•     C Model & test vector generator 
•     Simulation script, vectors & expected results; synthesis script 
•     User documentation 

The KEXP can be mapped to any ASIC technology. The following are sample pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

KEXP Standard Core ASIC Implementation Results

KEXP Fast Core ASIC Implementation Results

The KEXP can be mapped to any Altera FPGA device (provided sufficient silicon resources are available). The following are sample Altera results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

KEXP Standard Core Altera Implementation Results

KEXP Fast Core Altera Implementation Results

The KEXP can be mapped to any AMD FPGA device (provided sufficient silicon resources are available). The following are sample AMD FPGA results with all core I/Os assumed to be routed on-chip. The provided figures do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

KEXP Standard Core Xilinx Implementation Results

KEXP Fast Core Xilinx Implementation Results