A cache memory controller IP core available from semiconductor intellectual property provider CAST, Inc. brings cost- and resource-effective improvements in ...
Silicon IP Cores
Memory Controllers
Flash, Cache, & SRAM
A set of controller IP cores for different types of memories, including :
- xSPI-MC — A universal serial memory controller supporting NOR Flash, NAND Flash, and PSRAM Memories. Compatible to xSPI, Hyperbus, Xccela and most vendor-specific SPI protocols. Allows a system to easily detect and access an attached flash device, or directly boot from it.
- CACHE-CTRL — A flexible cache memory controller providing a 32-bit slave AHB-lite processor interface and a 32-bit master AHB-lite interface to the memory subsystem.
- SRAM-CTRL — An SRAM Controller translating AHB, or AXI4, or APB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM.
- ECC-SRAM — A core that adds Single-Error Correction / Dual Error Detection (SECDEC) to any SRAM, without altering its access latency
Each of these has been production-proven or rigorously verified, and comes with complete deliverables to simplify integration with your system.
Products in Family
xSPI, HyperBus™, and Xccela™ Serial Memory Controller
AHB Cache Controller
Static RAM Controller
Error Correcting Code for SRAMs