UDPIP-100G

100G UDP/IP Hardware Protocol Stack

The UDPIP-100G core receives and transmits UDP packet data, and forwards other traffic from the Ethernet MAC to the application and vice versa. It also receives and transmits ARP requests and responses, and responds to ICMP echo reply messages. The core generates and validates the UDP and IP checksums of outgoing and incoming packets, respectively. It can be programmed to discard or forward corrupted packets to the user application.

The core consists of the following modules:

The Ethernet Frame Decoder receives Ethernet frames from an external Ethernet MAC, detects the frame type and sends frames to the ARP or the IP packet decoder.

The Ethernet Frame Transmitter provides the external Ethernet MAC interface. The Transmitter also multiplexes ARP and IP transmit packets from the core subsystems.

The VLAN Receiver receives Ethernet frames from an ex-ternal Ethernet MAC, and when enabled detects and compares VLAN tag and filters frames to the correct VLAN tag. The VLAN Transmitter receives Ethernet frames from the Ethernet Frame Transmitter and adds the VLAN Tag to the frames when enabled.

The Protocol Decoder and Checker receives IP packets and handles them according to the packet type. The module decodes ICMP/IGMP/UDP/IP Packet types and saves the packets to the related receive packet buffer. The module also checks packets for errors.

The Received Packet Buffers implement separate data storage for each protocol and UDP channels. The buffers are implemented if the related protocol or UDP channel is enabled. The buffer sizes are configurable at synthesis time.

The Transmit Packet Buffer stores UDP application data as well as the ICMP and IGMP packet data. The size of the buffer is configurable at synthesis time.

The Transmit Packet Generator assembles ICMP, IGMP, UDP packets based on data received from the Transmit Packet Buffer.

The ARP Module sends and receives ARP packets and han-dles the packets according to command in the packet.

The DHCP Module automatically requests and acquires an IP address from a DCHP server.

Finally, the Control and Status Registers control the core's functionality and reports its status.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.

UDPIP-100G reference designs have been evaluated in a variety of technologies. The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and device.

Table 1: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support disabled.

UDPIP-100G reference designs have been evaluated in a variety of technologies. The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and device.

Table 1: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support enabled.

Table 2: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support disabled.

UDPIP-100G reference designs have been evaluated in a variety of technologies. The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and device.

Table 1: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support enabled.

Table 2: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support disabled.