An introduction to Time-Sensitive networking (TSN) and how it makes Ethernet a suitable backbone for complex automotive and industrial systems.
Jun 22, 2019
Silicon IP Cores
TSN-SE
TSN Ethernet Switched Endpoint Controller
The TSN-SE implements a configurable controller meant to ease the implementation of switched endpoints for Time Sensitive Net-working (TSN) Ethernet networks. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).
The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. With cut-through switching and minimal buffering even at the Ethernet MAC level, the TSN-SE features extremely low and deterministic ingress and egress latencies and simplifies the development of time-aware applications. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements, and provides the system with timing information (timestamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or endpoint.
The TSN-SE uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via AXI-Streaming interfaces with 32-bit data buses. To further expedite and ease the implementation of customer applications, DMA engines providing access to the stream interfaces via a memory-mapped AXI4 master port, and software stacks supporting higher-layer protocols, such as IEEE 802.1Qcc, IEEE 802.1Qca and SNMP, are optionally available
The TSN-SE is designed with industry best practices and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.
Support
The TSN-SE is suitable for the implementation of TSN Ethernet Endpoints in daisy chained networks (e.g. ring topologies) requiring robust, low-latency, and deterministic communication. Such networks are used in automotive, industrial control, medical, and aero-space applications.
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The TSN-SE has been rigorously verified, hardware-validated and tested in real-life environments. It has also been tested and verified at TSN interoperability plugfests organized by the Labs Network Industry 4.0 (LNI 4.0) association and the Industrial Internet Consortium (IIC).
Deliverables
The core includes everything required for successful implementation:
- Verilog RTL source code or targeted FPGA netlist
- Testbenches
- Sample Simulation and Synthesis scripts
- Comprehensive Documentation
- Lightweight PTP stack
- Device driver for FreeRTOS and Linux
Reference FPGA designs with a freeRTOS example software stack with Command Line Interface can be made available on request.
TSN-SE can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available. It’s silicon resources requirements depend on its configuration and start from 200k Gates and 400k bits of SRAM. Please contact CAST to get characterization data for your target configuration and technology.
The TSN-SE can be mapped to any Altera® FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a typical core configuration. Please contact CAST to get characterization data for your target configuration and technology.
| Family/Device | Configuration* | ALMs | Memory (Mbits) |
|---|---|---|---|
| Cyclone V 5CSEBA6U19C6 |
64 Lookup Entries 4kB Ingress Mem 8 Traffic Classes 1k TC Queue Depth No Frame Preemption |
11,823 | 0.42 |
| Cyclone V 5CSEBA6U19C6 |
128 Lookup Entries 4kB Ingress Mem 8 Traffic Classes 1k TC Queue Depth Frame Preemption |
18,434 | 0.82 |
| Cyclone V 5CSEBA6U19C6 |
512 Lookup Entries 4kB Ingress Mem 8 Traffic Classes 1k TC Queue Depth Frame Preemption |
24,358 | 1.50 |
*Partial list of configuration parameters
The TSN-SE can be mapped to any AMD FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a small number of core configurations. Please contact CAST to get characterization data for your target configuration and technology.
| Family/Device | Configuration* | Logic | Memory |
|---|---|---|---|
| Kintex 7 XC7k325-2 |
64 Lookup Entries 16kB Ingress Mem 4 Traffic Classes 1k TC Queue Depth No Frame Preemption |
12,253 LUTs | 30 RAMB36 22 RAMB18 |
| Kintex 7 XC7k325-2 |
256 Lookup Entries 16kB Ingress Mem 4 Traffic Classes 1k TC Queue Depth No Frame Preemption |
14,922 LUTs | 57 RAMB36 23 RAMB18 |
| Kintex 7 XC7k325-2 |
64 Lookup Entries 16kB Ingress Mem 8 Traffic Classes 1k TC Queue Depth No Frame Preemption |
17,941 LUTs | 64 RAMB36 31 RAMB18 |
| Kintex UltraScale XCKU035-1-c |
256 Lookup Entries 16kB Ingress Mem 8 Traffic Classes 1k TC Queue Depth No Frame Preemption |
17,320 LUTs | 64 RAMB36 31 RAMB18 |
| Kintex 7 XC7k70t-1 |
128 Lookup Entries 2kB Ingress Mem 4 Traffic Classes 1k TC Queue Depth Frame Preemption |
23,533 LUTs | 38 RAMB36 16 RAMB18 |
| Kintex 7 XC7k70t-1 |
256 Lookup Entries 2kB Ingress Mem 8 Traffic Classes 1k TC Queue Depth Frame Preemption |
31,858 LUTs | 91 RAMB36 25 RAMB18 |
| Kintex UltraScale XCKU115-2-I |
4k Lookup Entries 8kB Ingress Mem 8 Traffic Classes 1k TC Queue Depth Frame Preemption |
78,176 LUTs | 538 RAMB36 20 RAMB18 |
*Partial list of configuration parameters
The TSN-SE can be mapped to any Lattice FPGA device (provided sufficient silicon resources are available). The FPGA resources requirements depend on the core configuration. The following are sample results for a small number of core configurations. Please contact CAST to get characterization data for your target configuration and technology.
| Family/Device | Configuration | Logic | Memory |
|---|---|---|---|
| CertusPro-NX LFCPNX-100 |
64 Lookup Entries 512 Ingress Mem 2 Traffic Classes 1k TC Queue Depth No Frame Preemption |
15,676 LUT4 | 59 EBR |
| Certus-NX LFD2NX-40 |
64 Lookup Entries 512 Ingress Mem 2 Traffic Classes 1k TC Queue Depth No Frame Preemption |
15,676 LUT4 | 59 EBR |
| CertusPro-NX LFCPNX-100 |
512 Lookup Entries 512 Ingress Mem 8 Traffic Classes 1k TC Queue Depth Frame Preemption |
34,655 LUT4 | 208 EBR |
| Certus-NX LFD2NX-40 |
512 Lookup Entries 512 Ingress Mem 8 Traffic Classes 1k TC Queue Depth Frame Preemption |
66,698 LUT4 | 84 EBR |
Engineered by Fraunhofer IPMS.
Features List
TSN Ethernet Switched Endpoint
- Two Ethernet ports & one host processor port
- Suitable for daisy-chained networks such as rings
- 10/100/1000 Mbps (10Gbps soon)
Low Latency & Flexible Switching
- Low-latency Layer-2 Cut-Through Switching
- Run-time switch configuration enables fast response to network changes
- 802.1Q Tagged VLAN support
- Port-based VLAN
- Configurable VLAN-PCP to TSN-Queue Mapping (QoS by PCP)
- Flexible VLAN and MAC forwarding & filtering
- Configurable MAC lookup table for dynamic and static entries & automatic aging table
- Untagged ports support
- Port Statisitics
TSN Features
- Ready for IEEE 802.1AS-2020 (requires light-weight software stack)
- Traffic shaping per IEEE 802.1Qav & IEEE 802.1Qbv with eight TSN-Queues
- Frame preemption per IEEE 802.1Qbu and IEEE 802.3br
- Frame Replication and Elimination per IEEE 802.1CB and Per-Stream Filtering and Policing per IEEE 802.1Qci optionally implemented in hardware
- Path Control and Reservation per IEEE 802.1Qca, and Enhancements to Stream Reservation Protocol per EEE 802.1Qcc optionally implemented in software
Easy System Integration
- AMBA™/AXI4 SoC Interfaces
- 32-bit APB control/status interface
- 32-bit AXI4-Stream for packet data
- Optional AXI4 DMA engine
- MII, GMII or RGMII, and MDIO Ethernet PHY interface per port
- Requires minimal host assistance for the PTP stack, or no assistance from the host processor when licensed pre-integrated with an embedded processor
- Complete FPGA reference designs available