Silicon IP Cores
The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers. The core integrates an 8051 CPU with a serial communication controller, flexible timer/counter, multi-purpose I/O port, interrupt controller, and optionally with a debug unit supporting JTAG and Single-Wire interfaces.
The MCU executes some 8051 instructions in a single clock cycle, thus providing 0.1235 DMIPS/MHz (using the IAR Compiler) or 7.94x the performance per MHz of the original IntelTM 8051. Furthermore, the core can run at frequencies over 800MHz on a 40nm technology, offering performance that is almost 900x that of the original 8051.
The T8051XC3 runs the legacy code of existing systems, but is also ready for highly productive new software development. This is facilitated through CAST’s on-chip debugging option, and debug pods that cooperate with the Keil μVision C51 and IAR Embedded Workbench for 8051 IDEs.
This T8051XC1 IP core builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. It is rigorously verified, scan-ready, and available in source-code RTL or targeted FPGA netlist. Designed for easy reuse in ASICs or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional module), synchronous/asynchronous reset (user-selectable), and no internal tristates.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The following are sample ASIC pre-layout results and do not represent the absolute highest speed or smallest area possible. (Area figures do not include memories.)
Please contact CAST to get characterization data for your target configuration and technology.
| Technology | Clock Frequency | Area | |
| T8051XC3–CPU (CPU-only) | 40nm | 815 MHz | 4,015 eq. Gates |
| T8051XC3 (CPU, peripherals, no-OCDS) | 40nm | 815 MHz | 6,582 eq. Gates |
Engineered by Silesia Devices.
Code and debug this 8051 with these popular IDEs:
IAR Systems Embedded Workbench for 8051
These tools work with an optional, native on-chip debug block and inexpensive external adapter (pod) with a JTAG four-wire or SWAT Single-Wire PC interface.
Easily evaluate this 8051's features and performance in your own environment with the
Talos Series Evaluation Kit for 8051s.
Understanding Interrupt Latency in Modern 8051s
by Nikos Zervas at ChipEstimate.com