SPMI-CTRL
MIPI SPMI Controller or Target

SPMI-CTRL Block Diagram

The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either controller or target nodes in an SPMI bus.

The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check address and data parity. 

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Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host, which can be used for a higher application layer or for debugging purposes. Last received command, outgoing command status, bus status, and node operation status are made available to the host via the core’s registers. Parity errors, unknown commands, or failure of receiving node to provide ACK/NACK response are also reported. Furthermore, the core can be programmed to operate in debug mode, under which the core captures and reports all SPMI bus commands regardless of the destination address. 

Integration of the core is extremely simple: The core provides access to its registers via a AMBA™ 2 APB target interface, and converts the incoming SPMI read/write commands to accesses on its AHB controller port. This SPMI-AHB bridging allows easy mapping of the SPMI address space to shared memories or peripheral registers. A dedicated interface allows integration with application specific authentication logic, which can be reduced to just hardwiring the authentication response data. The core uses separate clocks for its APB and AHB bus interfaces, and a separate reference clock source for its internal timer. Clocks are independent to each other, with clean clock domain crossing boundaries, and the only requirement is that the AMBA interface clocks have a frequency larger or equal to the maximum SPMI clock frequency.
 
The core is designed with industry best practices, and its reliability has been proven through rigorous verification. 

The SPMI-CTRL can be mapped to any ASIC technology or FPGA device. The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Configuration Technology Area Max. Serial Clock
Arbitration-Capable Master TSMC 28nm HPC< 5,740 eq. Gates 26 MHz
Request-Capable Slave TSMC 28nm HPC 5,450 eq. Gates 26 MHz

The SPMI-CTRL can be mapped to any AMD FPGA device, provided sufficient resources are available. The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target device and technology

Configuration Device Family Logic Resources Max. Serial Clock
Arbitration-Capable Master Spartan-7, Artix-7, Kintex-7 880 LUTs 26 MHz
Arbitration-Capable Master Kintex & Virtex Ultrascale 830 LUTs 26 MHz
Request-Capable Slave Spartan-7, Artix-7, Kintex-7 750 LUTs 26 MHz
Request-Capable Slave Kintex & Virtex Ultrascal 690 LUTs 26 MHz

The SPMI-CTRL can be mapped to any Intel® FPGA device. The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target device and technology.

Configuration Device Family Logic Resources Max. Serial Clock
Arbitration-Capable Master Max® 10 1,870 LEs 26 MHz
Arbitration-Capable Master Startix® 10, Arria® 10 860 ALMs 26 MHz
Request-Capable Slave Max® 10 2,160 LEs 26 MHz
Request-Capable Slave Startix® 10, Arria® 10 1,065 ALMs 26 MHz

The SPMI-CTRL can be mapped to any Lattice FPGA device, provided sufficient resources are available. The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target device and technology

Configuration Device Family Logic Resources Max. Serial Clock
Non-Arbitration-Capable Master ECP5 1,269 LUT4s / 646 Slices 26 MHz
Request-Capable Slave ECP5 2,556 LUT4s / 1,296 Slices 26 MHz
Non-Request-Capable Slave ECP5 1,188 LUT4s / 610 Slices 26 MHz
Arbitration-Capable Master MachXO2 2,724 LUT4s / 1,375 Slices 26 MHz
Non-Arbitration-Capable Master MachXO2 1,274 LUT4s / 644 Slices 26 MHz
Arbitration-Capable Master iCE40 HX 3,237 LUTs / 3,247 LCs 26 MHz
Non-Arbitration-Capable Master iCE40 HX 1,474 LUTs / 1,477 LCs 26 MHz
Request-Capable Slave iCE40 HX 2,893 LUTs / 2,808 LCs 26 MHz
Non-Request-Capable Slave iCE40 HX 1,346 LUTs / 1,346 LCs 26 MHz

The SPMI-CTRL can be mapped to any Microchip FPGA device, provided sufficient resources are available. The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target device and technology

Configuration Device Family Logic Resources Max. Serial Clock
Arbitration-Capable Master PolarFile 2,727 4LUTs / 805 DFFs 26 MHz
Non-Arbitration-Capable Master PolarFile 1,331 4LUTs / 464 DFFs 26 MHz
Request-Capable Slave PolarFile 2,711 4LUTs / 750 DFFs 26 MHz
Non-Request-Capable Slave PolarFile 1,237 4LUTs / 367 DFFs 26 MHz
Arbitration-Capable Master IGLOO2 2,805 4LUTs / 805 DFFs 26 MHz
Non-Arbitration-Capable Master IGLOO2 1,345 4LUTs / 464 DFFs 26 MHz
Request-Capable Slave IGLOO2 2,721 4LUTs / 750 DFFs 26 MHz
Non-Request-Capable Slave IGLOO2 1,222 4LUTs / 367 DFFs 26 MHz
Arbitration-Capable Master ProASIC3 5,332 CORE / 808 SEQ 26 MHz
Non-Arbitration-Capable Master ProASIC3 2,658 CORE / 468 SEQ 26 MHz
Request-Capable Slave ProASIC3 4,939 CORE / 809 SEQ 26 MHz
Non-Request-Capable Slave ProASIC3 2,444 CORE / 395 SEQ 26 MHz

Related Content

Features List

MIPI-SPMI v2.0 Controller or Target

  • Supports High Speed (HS) and Low Speed (LS) device classes
    • Serial clock frequencies from 32kHz to 26MHz
  • Supports all commands, including Block, Extended and Extended Long Read/Writes
  • Supports all arbitration levels. Suitable for multi-controller and/or multi-target busses.
  • Configurations: 
    • Arbitration-Capable Controller
    • Non-Arbitration-Capable Controller
    • Request-Capable Target 
    • Non-Request-Capable Target

Low Host Overhead

  • Autonomously performs bus initialization, bus connect/disconnect, and bus arbitration
  • Autonomously executes all incoming SPMI commands, and generates ACK/NACK responses
  • Host is only required to: a) initialize register values after a reset b) define outgoing commands and arbitration levels and c) optionally respond to reported errors

Run-time Debugging Features

  • Broadcasts SPMI bus state and device state
  • Detects and reports parity, bus or command errors
  • Under debug mode captures all traffic in the SPMI bus
  • Run-time programmable identifiers (Controller, Target and up to 6 Group Target Identifiers per device)

Easy Integration

  • Directly bridges SPMI and AHB bus address space, allowing SPMI address space mapping either to a shared memory or directly to peripheral registers
  • Register access via 32-bit AMBA™ 2 APB bus

Small and Low Power

  • Less than 6,000 Gates for either the controller or the target core
  • Direct serial clock usage to minimize switching activity when idle
SPMI-CTRL BRIEF (ASIC)
SPMI-CTRL BRIEF (ALTERA)
SPMI-CTRL BRIEF (AMD)
SPMI-CTRL BRIEF (LATTICE)
SPMI-CTRL BRIEF (MICROCHIP)

Resources

Additional Information

Related Products

I3C-T

MIPI I3C Basic Target

I3C-SC

MIPI I3C Basic Secondary Controller

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