UDPIP-10G/25G

10G/25G UDP/IP Hardware Protocol Stack

The UDPIP-10G/25G core receives and transmits UDP packet data, and forwards other traffic from the Ethernet MAC to the application and vice versa. It also receives and transmits ARP requests and responses, and responds to ICMP echo reply messages. The core generates and validates the UDP and IP checksums of outgoing and incoming packets, respectively. It can be programmed to discard or forward corrupted packets to the user application.

The core consists of the following modules:

The Ethernet Frame Decoder receives Ethernet frames from an external Ethernet MAC, detects the frame type, and sends frames to the ARP or the IP packet decoder. The Ethernet Frame Transmitter provides the external Ethernet MAC interface. The transmitter also multiplexes ARP and IP transmit packets from the core subsystems.

The VLAN Receiver receives Ethernet frames from an external Ethernet MAC, and when enabled detects and compares VLAN tag & filters frames to the correct VLAN tag. The VLAN Transmitter receives Ethernet frames from the Ethernet Frame Transmitter and adds the VLAN Tag to the frames when enabled. 

The Packet Receiver Module receives IP packets and handles them according to the packet type. The Packet Decoder receives IP packets and the decoded packets are stored in the Rx Packet Buffer and then passed to the user application.  The Received Packet Buffer implements separate data storage for the UDP application data and other data, and its size is configurable at synthesis time.

The Packet Transmit Module assembles UDP and ICMP packets. The UDP application data, as well as the ICMP packet data, are stored in the transmit buffer, the size of which is configurable at synthesis time.

The ARP Module sends and receives ARP packets and handles the packets according to command in the packet. The DHCP Module automatically requests and acquires an IP address from a DCHP server.

The UDP Channel Demultiplexer receives UDP packets and demultiplexes them according to a decoded UDP channel number. The UDP Channel Multiplexer receives UDP packet channels from a user application and multiplexes them to the Packet Transmitter module.

Finally, the Control and Status Registers control the core functionality and report the core status

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts, and comprehensive user documentation.

The UDPIP-10G/25G is a purely digital design that does not use any technology-specific modules and can, therefore, be mapped to any ASIC technology. The following table provides sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Table 1: UDPIP-10G/25G sample results for the core configured with ARP, ICMP, IGMP, Rx and Tx, and without DHCP and VLAN support

The UDPIP-10G/25G can be mapped to any Altera FPGA device (provided sufficient silicon resources are available). The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Table 1: UDPIP-10G/25G sample results for the core configured with ARP, ICMP, IGMP, 16kB Rx Buffers, 8kB Tx Buffers, and without DHCP and VLAN support

The UDPIP-10G/25G can be mapped to any AMD FPGA device (provided sufficient silicon resources are available). The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Table 1: UDPIP-10G/25G sample results for the core configured with ARP, ICMP, IGMP, 16kB Rx buffers, 8kB Tx buffers, and without DHCP and VLAN support

The UDPIP-10G/25G can be mapped to any Lattice FPGA device (provided sufficient silicon resources are available). The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Table 1: UDPIP-10G sample results for the core configured 20kB Rx buffers, 4kB Tx buffers, ARP, ICMP, IGMP, without DHCP and VLAN support

The UDPIP-10G/25G can be mapped to any Microchip FPGA device (provided sufficient silicon resources are available). The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Table 1: UDPIP-10G /25G sample results for the core configured with ARP, ICMP, IGMP, 16kB Rx Buffers, 8kB Tx Buffers, and without DHCP and VLAN support