PCI-M32
32-bit/33MHz PCI Master/Target

The PCI-M32 implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz PCI clock.

The PCI-M32 Interface has both Master and Target capabilities. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required.

The Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB. Both Target and Master supported commands are:

Configuration Read, Configuration Write
Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL)
I/O Read, I/O Write

The PCI-M32 builds on more than 15 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.

The core has been verified through extensive simulation and rigorous code coverage measurements.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:

HDL RTL source code for PCI-M32 Core
HDL RTL source code for DMA Controller
Sophisticated HDL Testbench
Simulation script, vectors, expected results, and comparison utility
Synthesis script
Comprehensive user documentation, including detailed specifications and a system integration guide

The PCI-M32 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample ASIC results with a single base address register and without a DMA. Please contact CAST to get characterization data for your target configuration and technology.

ASIC Device	Approx.Area	Frequency(MHz)
TSMC 65 nm	3,150 gates	66

The PCI-M32 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Intel Devices	LEs (single base address register configuration without DMA)	IOBs ( assuming all PCI only I/Os are routed off-chip)	Memory	Fmax (MHz)
Excalibur EPX4F672C1	635	51	-	33
Cyclone EP1C12F324C8	628	51	-	33
APEX EP20K100E-2	668	51	-	33

The PCI-M32 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results assuming that only the PCI I/Os are routed off-chip and the core is configured with a single base address register and without a DMA. Please contact CAST to get characterization data for your target configuration and technology.

Family	Device	LUTs	BRAM	DSP	Fmax (MHz)
Artix-7	7a100t-2	653	2	0	33
Kintex-7	7k160t-2	650	2	0	33

The PCI-M32 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample Microchip results configured with two BARs, DMA and an ALU example application. Please contact CAST to get characterization data for your target configuration and technology.

Microchip Device	Cells		Ram Blocks	I/Os	Fmax (MHz)
Microchip Device	Sequ (R)	Comb (C)	Ram Blocks	I/Os	Fmax (MHz)
RadTolerant RTAX250S-1	620	1530	4	50	33
Axcelerator AX250-1	620	1530	4	50	33
SmartFusion2 M2S150-STD	848 DFF	1632 4LUT	9	50	33
Igloo2 M2GL150-STD	848 DFF	1632 4LUT	9	50	33