L8051XC1

Legacy-Configurable 8051-Compatible Microcontroller IP

Three standard versions of the core are available, offering a range of capabilities and prices.

• L8051XC1-A includes options that match the original Intel 8051 peripheral set: 64KB memory interface, two timers, one serial port, four parallel I/O Ports, two-level interrupt controller, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
• L8051XC1-B includes options that match the Infineon 80515/80517 peripheral set: 64KB memory interface, three timers, two serial ports, four parallel I/O ports, watchdog timer, multiplication-division unit, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
• L8051XC1-C has custom/user-defined architectural and peripheral options. This version may integrate user-defined peripherals that are not supported by the automatic configuration tool. Please consult with your CAST sales contact to discuss your specific requirements and get lead time information.

ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.

The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models. An extensive constrained random verification was performed to verify the CPU, DMA and OCDS.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.

Deliverables

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation. ASIC versions include:

• HDL RTL source code 
• Easy-to-use configuration tool (with configurable versions)
• An example chip implementation, which uses the core in a sample system
• Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
• Simulation script, vectors, and expected results
• Synthesis script
• Comprehensive user documentation, including detailed specifications and a system integration guide

A reference design board is available; contact CAST Sales for information.
 

L8051XC1 designs have been evaluated in a variety of technologies. The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The target technology is TSMC 40nm.  Please contact CAST to get characterization data for your target configuration and technology.

The DMA requires an additional 1.5K gates per channel.

The provided figures do not represent the higher speed or smaller area for the core and area figures do not include any memories. Please contact CAST to get characterization data for your target configuration and technology.