JPEG-EX-S
Baseline and Extended JPEG Encoder

This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, ASIC or FPGA hardware JPEG encoder with very low processing latency. 

The JPEG-EX-S encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.  

The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it requires just 80,000 equivalent gates when mapped on an ASIC technology.  

Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface. 

Customers with a short time to market priority can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG encoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.  

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model. 

    The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies. 

    Support 

    The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

    Deliverables 

    The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The deliverable includes: 

    • Verilog RTL source code 
    • Sophisticated self-checking Testbench  
    • Software (C++) Bit-Accurate Model  
    • Sample simulation and synthesis scripts 
    • Comprehensive user documentation 

    The JPEG-EX-S core can be mapped to any ASIC and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. 

      UHD/4k
    30fps, 4:2:2
    UHD/4k
    30fps, 4:4:4
    UHD/4k
    60fps, 4:4:4
    Area
    (Kgates)
    Freq
    (MHz)
    TSMC 40g 83 500
    TSMC 28hpm 68 800
    TSMC 16 75 1,000


    Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology. 

    The JPEG-EX-S core can be mapped to any Altera Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. 

      1080p30
    4:2:2
    720p60
    4:4:4
    1080p60
    4:2:2
    Logic
    Resources
    DSPs Memory
    Bits
    Max10 10,746 LEs 8 51,901
    CycloneV 4,070 ALMs 4 52,458
    Arria10 3,999 ALMs 4 52,354


    Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology. 

    The JPEG-EX-S core can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. 

    Family /Device Logic Block RAMs DSP
    Comp.
    Fmax
    (MHz)
    ECP5U / LAE5U-12F 8.380 Slices
    12,945 LUT4s
    11 8 95


    Note that the implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology. 

    The JPEG-EX-S core can be mapped to any Xilinx Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. 

      1080p30
    4:4:4
    1080p60
    4:2:0
    1080p60
    4:2:2
    LUTs DSPs BRAMs
    Artix-7
    (speed grade -2)
    5,950 4 2.5
    Kintex7
    (speed grade -2)
    6,197 4 2.5
    Kintex7-US
    (speed grade -1)
    6,029 4 2.5


    Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology. 

    Related Content

    Features List

    Performs Baseline and Extended Sequential DCT JPEG encoding of images or video for ASICs or FPGAs, with small silicon area, high performance, and low latency. 

    Standards Support 

    • ISO/IEC 10918-1 Standard Baseline and Extended Sequential DCT modes 
    • Single-frame JPEG images and Motion JPEG payloads 
    • 8-bit and 12-bit per color samples 
    • Up to four color components; any image size up to 64k x 64k  
    • All scan configurations and all JPEG formats  
    • APP, COM, and restart markers 
    • Programmable Huffman Tables and Quantization tables  

    Rate Control Options 

    • Image: Limits the size of each individual frame 
    • Video: Regulates bit rate over a number of input frames. 

    Interfaces 

    • AXI Streaming I/O data interfaces 
    • APB Control/Status interface 

    Performance and Size 

    • One encoded sample per clock cycle 
    • Small silicon footprint (about 80k ASIC gates) 

    Ease of Integration 

    • Automatic program-once/encode-many operation 
    • Simple, dedicated timestamps interface  
    • Included bit-accurate software model generates test vectors, expected results, and core programming values 
    • Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer 

    Resources

    See the JPEG entry at Wikipedia.

    See the Motion JPEG entry at Wikipedia.

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