GZIP-RD-INT
GZIP & GUNZIP Acceleration Card Reference Design for Intel’s PAC board

The GZIP-RD-INT is a reference design for an FPGA PCIe data compression acceleration card. It uses the ZipAccel-C and ZippAccel-D GZIP/ZLIB/Deflate Compression and Decompression IP Cores.

The accelerator is highly efficient and can compress data at rates exceeding 40 Gbps, making it suitable for servers or databases where it optimizes storage requirements or network bandwidth.

The GZIP-RD-INT is available as a "drop-in" accelerator function for the Intel® Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA. Some of the off-the-shelf configurations for this board are shown below:

AFU Function

History Window

Huffman Tables

# Search / # Huffman

C/R1

Gbps1

Arria 10 GX 1150 Resources

ALMs

Mem.  Bits

Compression

32KB

Dynamic & Static

1/1

3.76

1.28

20%

17%

Compression

32KB

10/2

3.49

12

40%

49%

Compression

4KB

16/4

3.32

17.9

50%

38%

Compression

1KB

20/10

3.22

41

71%

56%

Compression

512B

Static

18/6

2.26

43.5

40%

34%

Decompression

32KB

Dynamic & Static

N/A

N/A

4.4

14%

3%

1: Compression Ratio and Throughput for the Canterbury Corpus

The reference design is delivered with a sample GUI-driven application, which designers can use to evaluate the performance of the ZipAccel-C and ZipAccel-D cores or as a basis to develop their own application. Intel’s DCP drivers facilitate integration with application software. The reference design pulls in frameworks and libraries using the Intel Acceleration Stack for Intel Xeon CPU with FPGAs, easing the use of FPGA acceleration in Xeon-based systems.

The ZipAccel-C and Zipaccel-D IP cores are highly configurable and can be tuned to meet different application requirements with respect to compression efficiency for specific data types, latency and throughput. CAST will work with you to define the IP cores’ configuration that meets your application requirements.

Deliverables include the firmware (FPGA programming file), software (drivers), and comprehensive documentation, but please note that the FPGA board has to be purchased separately.

For more information please contact CAST sales.

Related Content

Features List

PCIe board data compression reference design for ZipAccel-C Core evaluation or application development.

GZIP Acceleration

  • 40 Gbps (or higher upon request) uncompressed data rate
  • High compression efficiency (comparable to software gzip-6)
  • Fully Compliant to the GZIP  standard (RFC-1952)

Supported Hardware

  • Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA
  • Bitware A10PL4 (Intel Arria 10)
  • Reflex CES XpressGXA10-LP1150B (Intel Arria 10)
  • Design portable to other boards and FPGA families

Software Interface

  • Intel DCP Drivers
  • Works with libraries and frameworks using Intel Xeon Acceleration Stack for Xeon CPU with FPFAs

 

    Resources

    Info on Intel Xeon with FPGA:

    Applicable Standards

    Let's talk about your project and our IP solutions

    Request Info