ZipAccel-C
GZIP/ZLIB/Deflate Data Compressor

ZipAccel-C is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards. 

The core receives uncompressed input files and produces compressed files. No post processing of the compressed files is required, as the core encapsulates the compressed data payload with the proper headers and footers. Input files can be segmented, and segments from different files can be interleaved at the core’s input.
  
The core’s flexible architecture enables fine-tuning of its compression efficiency, throughput, and latency to match the requirements of the end application. Throughputs in excess of 100 Gbps are feasible even in FPGAs, and latency can be as small as a few tens of clock cycles.
 
ZipAccel-C offers compression efficiency practically equivalent to today’s popular deflate-based software applications. Analyzing processing speed versus compression efficiency to achieve the best trade off for a specific system is facilitated by the included software model, and by support from our team of data compression experts. 

ZipAccel-C has been designed for ease of use and integration. It operates on a standalone basis, off-loading the host CPU from the demanding task of data compression, and optionally from the task of encrypting the compressed stream. Streaming data interfaces and optional AMBA bus interfaces ease SoC integration. 

Technology mapping is straightforward, as the design is scan-ready, microcode-free, and uses easily replaceable, generic memory models. Memory blocks can optionally support Error Correction Codes (ECC) to simplify achievement of Enterprise Class reliability requirements. Furthermore, input file segmentation can limit the inter-file latency and helps users achieve Quality of Service (QoS) objectives. 
 

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:

  • HDL (Verilog) RTL source code
  • Sophisticated Test Environment
  • Simulation scripts, test vectors and expected results
  • Synthesis script
  • Comprehensive user documentation

ZipAccel-C reference designs have been evaluated in a variety of technologies. ZipAccel-C performance can scale by instantiating more search engines and/or Huffman encoders. Furthermore, other design options such as the search area window affect the silicon resources utilization. 

Over 100 Gbps throughputs are feasible, and the silicon footprint can be less than 100KGates. Contact CAST Sales for help defining likely configuration options and estimating implementation results for your specific system.

The ZipAccel-C can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The ZipAccel-C performance can scale by instantiating more search engines and/or Huffman encoders. Furthermore, other design options such as the search area window affect the silicon resources utilization. The following table provides sample Intel  results for a subset of the possible configuration options. They do not represent the smallest possible area requirements nor the highest possible clock frequency. Please contact CAST to get characterization data for your target configuration and technology.

Family Configuration ALMs RAM Bits
Stratix V 1 Search Engine, I Dynamic Huffman Encoder, 4KB History Window, 200MHz 10,768 781,294
Stratix V 4 Search Engines, I Dynamic Huffman Encoder, 4KB History Window, 200MHz 26,840 3,886,517
Stratix V 32 Search Engines, 4 Dynamic Huffman Encoders, 4KB History Window, 200MHz 240,969 32,370,088

TheZipAccel-C can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). ZipAccel-C performance can scale by instantiating more search engines and/or Huffman encoders. Furthermore, other design options such as the search area window affect the silicon resources utilization. The following table provides sample Xilinx results for a subset of the possible configuration options. They do not represent the smallest possible area requirements nor the highest possible clock frequency. Please contact CAST to get characterization data for your target configuration and technology.

Family / Device Configuration LUts RAM Blocks

Kintex-7

xc7k325-2
1 Search Engine, I Dynamic Huffman Encoder, 4KB History Window, 150MHz 14,549 52

Kintex-7

xc7k325-2
8 Search Engines, 2 Dynamic Huffman Encoders, 4KB History Window, 150MHz 86,172 411

Virtex-7

xc7v690-2
16 Search Engines, 4 Dynamic Huffman Encoders, 8KB History Window, 200MHz 207,375 1292

Virtex-7

xc7v1149-2
32 Search Engines, 8 Dynamic Huffman Encoders, 4KB History Window, 200MHz 380,892 1,512

Related Content

Features List

Compression Standards 

  • Deflate (RFC-1951)
  • ZLIB (RFC-1950)
  • GZIP (RFC-1952)

Deflate Features

  • LZ77 with configurable block and search window size
  • Static and Dynamic Huffman
  • Optional Stored Deflate Blocks 
  • Dynamic Mode Selection 

Flexible Architecture 

  • Fine-tune Throughput, Compression Efficiency, and Latency to match application requirements
    • More than 100Gbps with one core instance, scalable to meet any throughput requirement 
    • Compression efficiency can be on par with Unix/Linux max compression option (gzip -9)  
    • Silicon requirements start from less than 100k gates
    • Under 40 clock cycles for Static Huffman 
  • Configuration Options (partial list):
    • Search Engine and Huffman Encoder Architecture
    • History Search Window Size (up to 32KB)
    • Deflate Block Size
    • Stored Blocks Support
    • Parallel Processing Level

Easy to Use and Integrate

  • Processor-free, standalone operation  
  • Streaming-capable interfaces and optional AMBA bus wrappers
  • Large file segmentation enables meeting QoS objectives
  • Microcode-free, scan-ready design
  • Optional ECC memories, necessary for Enterprise-Class RAMs  
  • Optionally integrated with encryption or other cores from CAST
  • Complete, turn-key Accelerator Designs available on FPGA boards from different vendors

Resources

Applicable Standards
RFC 1952 – GZIP file format
 RFC 1950 – ZLIB Compressed Data Format
• RFC 1951 – DEFLATE Compressed Data Format
Background & More Info
Data Compression in Solid State Storage, presentation at Flash Memory Summit 2013 (PDF)
• Wikipedia entries on GZIP, ZLIB, and Deflate
• An explanation of the Deflate algorithm by Antaeus Feldspar
GZIP Project website
ZLIB Project website

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