JPEG-DX-F
Ultra-Fast Baseline and Extended JPEG Decoder

This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements a scalable, ultra-high-performance, ASIC or FPGA, hardware JPEG decoder that handles extremely high pixel rates.  

The JPEG-DX-F Decoder decompresses JPEG images and the video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats.  

Depending on its configuration, the decoder processes from two to 32 color samples per clock cycle. Its high throughput capabilities are best exploited when decompressing streams produced by the JPEG-EX-F Encoder Core. This Encoder-Decoder pair provide an extremely cost-effective solution for streaming or archiving UHD (4K/8K) video, or very high frame rates at lower resolutions.  

Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed. 

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.  

Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.  

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model. 

 

 

 

    The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies. 

    Support 

    The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

    Deliverables 

    The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes: 

    • Verilog RTL source code 
    • Sophisticated self-checking Testbench  
    • Software (C++) Bit-Accurate Model 
    • Sample simulation and synthesis scripts 
    • Comprehensive user documentation

    The silicon resources requirements for the JPEG-DX-F decoder core depend on its configuration. A two samples per cycle configuration synthesizes to approximately 110K gates and requires 50k-bits of memory. 

    The JPEG-DX-F can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data the core configured to process 2 pixels per cycle (JPEG-DX-F/2) and under its default configuration.  

    JPEG-DX-F/2

    1080p30
    4:2:2

    1080p60
    4:2:2

    UHD/4k
    30fps, 4:2:0

    Logic
    Resources
    MULTs/DSPs

    Memory
    Bits

    Max10
     

     

     

     

    16,500 LEs

    20

    76,928

    CycloneV
     

     

     

     

    6,700 ALMs

    10

    77,010

    Arria10
     

     

     

     

    6,700 ALMs

    10

    77,010

    StratixV

     

     

     

    6,700 ALMs

    10

    77,010


    Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology. 

    The JPEG-DX-F can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data the core configured to process 2 pixels per cycle (JPEG-DX-F/2) and under its default configuration. 

    Family / Device Logic

    Block
    RAMs

    DSP
    Comp.

    Fmax
    (MHz)

    ECP5U / LAE5U-12F

    18.250 LUT4s
    12,904 Slices

    18 16 70


    Note that the implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology. 

    The JPEG-DX-F can be mapped to any Xilinx Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data the core configured to process 2 pixels per cycle (JPEG-DX-F/2) and under its default configuration.  

    JPEG-DX-F/2 1080p30 
    4:2:2
    1080p60 
    4:2:2
    UHD/4k
    30fps, 4:2:0
    LUTs DSPs BRAMs

    Artix-7 (-2)

          11,650 10 6 RAMB16

    Kintex7 (-2)

          10,650 10 5 RAMB16

    Kintex7-US (-1)

          10,200 10 7 RAMB16


    Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology. 

    Related Content

    Features List

    8/12-bit JPEG decoder for ASIC and FPGA with scalable, ultra-high performance 

    Standards Support 

    • ISO/IEC 10918-1 Standard Baseline and Extended Decoder  (Sequential DCT modes) 
    • Single-frame JPEG images and Motion JPEG payloads 
    • Up to four color components 
    • 8- and 12-bit color samples 
    • All widely used color subsampling formats, and any image size up to 64k x 64k  
    • All scan configurations and all JPEG formats  
    • All marker segments expect DNL 
    • Up to four Huffman Tables  
    • Up to four 8-nit or 16-bit Quantization tables  

    Interfaces 

    • AXI Streaming I/O data interfaces 
    • APB Control/Status interface 
    • Optional AHB wrapper with DMA capabilities 

    Performance 

    • Synthesis-time configurable scalable architecture 
    • Very high throughput: up to 32 samples per clock cycle  
    • Achieves maximum throughput when decoding streams produced by JPEG-EX-F  

    Ease of Integration 

    • Requires no programming or control from host  
    • Reports image format 
    • Detects and reports marker syntax errors 
    • Delivered with bit-accurate software model  
    • Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer 

    Resources

    See the JPEG entry at Wikipedia.

    See the Motion JPEG entry at Wikipedia.

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    This core implements encryption functions and as such it is subject to export control regulations. Export to your country may or may not require a special export license. Please contact CAST to determine what applies in your specific case.