Silicon IP Cores
The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard.
It decompresses JPEG images, and also video payload for Motion-JPEG container formats. It supports 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. The decoder processes one color sample per clock cycle, enabling it to process multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG decoders available, it requires just 76,000 equivalent gates when mapped on an ASIC technology.
Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. The decoder reports the image format (i.e., resolution, subsampling format, and color sample-depth) to the system, so that the decoded images are properly further processed and/or displayed.
SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access.
Customers with a short time to market requirements can use CAST’s IP Integration Services to receive complete JPEG subsystems. These integrate the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST.
The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products and is proven in both ASIC and FPGA technologies.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms and includes everything required for successful implementation. The ASIC version includes:
The JPEG-DX-S core synthesizes to approximately 75K gates and requires 25k bits of memory.
The JPEG-DX-S can be mapped to any Intel FPGA Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core.
| 720p60 4:2:0 |
1080p30 4:2:2 |
1080p60 4:2:0 |
Logic Resources |
MULTs/DSPs |
Memory |
|
|---|---|---|---|---|---|---|
|
Max10 |
|
|
|
10,400 LEs |
10 |
33,344 |
|
CycloneV |
|
|
|
4,200 ALMs |
5 |
33,498 |
|
Arria10 |
|
|
|
4,200 ALMs |
5 |
33,498 |
|
StratixV |
|
|
|
4,200 ALMs |
5 |
33,498 |
Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology.
The JPEG-DX-S can be mapped to any AMD Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core.
|
720p60 |
1080p30 |
1080p60 |
LUTs | DSPs | BRAMs | |
|---|---|---|---|---|---|---|
|
Artix-7 (-2) |
7,500 | 5 | 1 RAMB16 | |||
|
Kintex7 (-2) |
6,500 | 5 | 2 RAMB16 | |||
|
Kintex7-US (-1) |
5,350 | 5 | 3 RAMB16 |
Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to get characterization data for your target configuration and technology.
The JPEG-DX-S can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core.
| Family / Device | Logic |
Block |
DSP |
Fmax |
|---|---|---|---|---|
| ECP5U / LAE5U-12F |
11.843 LUT4s |
9 | 8 | 70 |
Note that the implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology.
Engineered by Beyond Semiconductor.
Area-efficient, high-performance 8/12-bit JPEG decoder for ASICs and FPGAs
See the JPEG entry at Wikipedia.
See the Motion JPEG entry at Wikipedia.