JPEG-E-T
Tiny Baseline JPEG Encoder

This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, hardware JPEG encoder with very low processing latency. Probably the smallest JPEG encoder IP core in the marker, the JPEG-EX-T occupies about 40,000 equivalent NAND2 gates. 

The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. Once programmed, the easy-to-use encoder requires no assistance from a host processor to compress an arbitrary number of frames. 

SoC integration is straightforward thanks to standardized AMBA® interfaces: AXI Streaming for pixel and compressed data, and a 32-bit APB slave interface for registers access. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface. 

The core is designed with industry best practices, and its reliability and low risk have been proven through both rigorous verification and customer production. Its deliverables include a complete verification environment and a bit-accurate software model.
 

Verification

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available as a targeted FPGA netlist, and includes everything required for successful implementation:
•    Sophisticated self-checking Testbench 
•    Software (C++) Bit-Accurate Model 
•    Sample simulation and synthesis scripts
•    Comprehensive user documentation
 

The JPEG-E-T core can be mapped to any Xilinx Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core. 

  1080p30
4:4:4
1080p60
4:2:0
1080p60
4:2:2
LUTs DSP BRAMs
Artix-7 
(speed grade -3)
2,923 16 3
Kintex7
(speed grade -3)
3,011 16 3
Kintex7-US
(speed grade -2)
2,969 16 3


Note that the list of video formats is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please contact CAST to discuss silicon resource utilization and performance for your target technology. 

The JPEG-E-T core can be mapped to any Altera Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation and performance data for the default configuration of the core.

  1080p30
4:2:2
720p60
4:4:4
1080p60
4:2:2
Logic
Resources
DSP Memory
Bits
Max10 8,750 LEs 8 17,756
Cyclone10 8,748 ALMs 8 17,756
Arria10 3,293 ALMs 4 18,102

Related Content

Features List

Extremely small JPEG encoder 

Standards Support

  • ISO/IEC 10918-1 Standard Baseline Encoder (Sequential DCT modes)
  • Encodes single-frame JPEG images and Motion JPEG payloads
  • 8-bit or 12-bit color samples
  • Up to four color components; any image size up to 64k x 64k 
  • Handles all scan configurations and all JPEG formats 
  • APP, COM, and restart markers
  • Programmable Quantization table, for image quality or bit rate control

Interfaces

  • AXI Streaming input and output data interfaces
  • APB Control/Status interface
  • Optional AHB wrapper with DMA capabilities

Performance and Size

  • One encoded sample per clock cycle
  • Small silicon footprint (40,000 Gates)

Ease of Integration

  • Automatic program-once/encode-many operation
  • Simple, dedicated timestamps interface 
  • Included bit-accurate software model generates test vectors, expected results, and core programming values
  • Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer

Format

  • Available as a targeted netlist for ASICs or FPGAs

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