UDPIP-100G
100G UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 100Gbps even in processor-less SoC designs. 

Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN. 

The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or optionally via registers mapped on an SoC bus. Up to 32 streaming interfaces are used for transmit data, and up to 32 for receive data. Each such pair of receive and transmit interfaces (a  “channel”) is configured independently, with the source UDP port, destination IP address and UDP port, multicast receive address and transmit mode (unicast or multicast). The AMBA® AXI4-stream or the Avalon®-ST streaming protocols and the AMBA AHB and AXI, Avalon-MM, or Wishbone SoC bus protocols are supported. 
 

The UDPIP-100G core receives and transmits UDP packet data, and forwards other traffic from the Ethernet MAC to the application and vice versa. It also receives and transmits ARP requests and responses, and responds to ICMP echo reply messages. The core generates and validates the UDP and IP checksums of outgoing and incoming packets, respectively. It can be programmed to discard or forward corrupted packets to the user application.

The core consists of the following modules:

The Ethernet Frame Decoder receives Ethernet frames from an external Ethernet MAC, detects the frame type and sends frames to the ARP or the IP packet decoder.

The Ethernet Frame Transmitter provides the external Ethernet MAC interface. The Transmitter also multiplexes ARP and IP transmit packets from the core subsystems.

The VLAN Receiver receives Ethernet frames from an ex-ternal Ethernet MAC, and when enabled detects and compares VLAN tag and filters frames to the correct VLAN tag. The VLAN Transmitter receives Ethernet frames from the Ethernet Frame Transmitter and adds the VLAN Tag to the frames when enabled.

The Protocol Decoder and Checker receives IP packets and handles them according to the packet type. The module decodes ICMP/IGMP/UDP/IP Packet types and saves the packets to the related receive packet buffer. The module also checks packets for errors.

The Received Packet Buffers implement separate data storage for each protocol and UDP channels. The buffers are implemented if the related protocol or UDP channel is enabled. The buffer sizes are configurable at synthesis time.

The Transmit Packet Buffer stores UDP application data as well as the ICMP and IGMP packet data. The size of the buffer is configurable at synthesis time.

The Transmit Packet Generator assembles ICMP, IGMP, UDP packets based on data received from the Transmit Packet Buffer.

The ARP Module sends and receives ARP packets and han-dles the packets according to command in the packet.

The DHCP Module automatically requests and acquires an IP address from a DCHP server.

Finally, the Control and Status Registers control the core's functionality and reports its status.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.

UDPIP-100G reference designs have been evaluated in a variety of technologies. The following are sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not rep-resent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and device.

UDP
Channels
ASIC
Technology
Eq. NAND2
gates
Freq.
(MHz)
SRAM .
Memory
1 TSMC 7nm 178k 125 80kB
4 TSMC 7nm 338k 125 176kB
8 TSMC 7nm 175k 125 304kB
16 TSMC 7nm 338k 125 560kB

Table 1: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support disabled.

UDPIP-100G reference designs have been evaluated in a variety of technologies. The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and device.

Family /
Device
UDP
Channels
ALMs RAM
Blocks
Freq.
(MHz)
Arria 10 GX
10AX115S2F5E1SG
1 12,496 79 250
4 17,960 118
8 23,340 170
16 35,619 274
Stratix-10GX
1SG250LN3F43E1VG
1 14,652 79 250
4 21,113 118
8 28,241 170
16 43,968 274

Table 1: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support enabled.

Family /
Device
UDP
Channels
ALMs RAM
Blocks
Freq.
(MHz)
Arria 10 GX
10AX115S2F5E1SG
1 9,127 53 250
4 13,902 92
8 19,088 144
16 31,123 248
Stratix-10GX
1SG250LN3F43E1VG
1 11,165 53 250
4 16,712 92
8 24,078 144
16 38,834 248

Table 2: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support disabled.

UDPIP-100G reference designs have been evaluated in a variety of technologies. The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and device.

Family /
Device
UDP
Channels
LUTs BRAM
Tiles
Freq.
(MHz)
Kintex Ultrascale
Xcku060-2-e
1 13,611 45 250
4 16,864 68
8 22,232 98
16 32,774 159
Zynq UltraScale+
xczu11eg-1-e
1 13,575 45 250
4 16,816 68
8 22,184 98
16 32,718 159

Table 1: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support enabled.

Family /
Device
UDP
Channels
LUTs BRAM
Tiles
Freq.
(MHz)
Kintex Ultrascale
Xcku060-2-e
1 9,929 30 250
4 13,6214 53
8 18,011 83
16 27,341 143
Zynq UltraScale+
xczu11eg-1-e
1 9,928 30 250
4 13,620 53
8 18,011 83
16 27,337 143

Table 2: UDPIP-100G Sample Results for the core configured with 32kB transmit and receive buffers, and the Statistics Counters, Multicast. VLAN, and DHCP support disabled.

Related Content

Features List

Complete UDP/IP Hardware Stack

  • 1/10/40/100G Ethernet
  • IPv4 support without packet fragmentation
  • Jumbo and Super Jumbo Frames
  • Transmit and Receive
  • ARP with Cache
  • ICMP (Ping Reply)
  • IGMP v3 (Multicast)
  • UDP/IP Unicast, and Multicast
  • UDP Port Filtering
  • UDP/IP Checksums generation and validation, and optional Ethernet CRC validation
  • VLAN (IEEE 802.1Q) support
  • 1 to 32 UDP transmit and 1 to UDP 32 receive channels
  • Ethernet Framing processing for non-UDP user-provided packets
  • DHCP client

Trouble-Free Operation

  • Run time programmable network parameters:
    • Local MAC address, Local IP address, Gateway IP address, and IP subnet mask
    • Per channel: Destination IP address, Source and Destination and filtered UDP ports, multicast enable/disable and receive group
  • ARP support for operation in networks with Dynamic IP allocation

Easy SoC Integration

  • Flexible interfaces:
    • Packet Data: 512-bit streaming capable using Avalon-ST or AXI4-Stream
    • Control/Status Registers: Generic 32-bit SRAM-like, or optionally 32-bit AHB, AXI, Avalon-MM or Wishbone
  • Separate clock domains for packet processing and control/status interfaces
  • Configurable buffer sizes
  • Rich interrupt support for system events

 

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