UDPIP-1G/10G
UDP/IP Hardware Protocol Stack

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 10Gbps even in processor-less SoC designs. 

Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address, etc). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity.  It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN.

The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated AMBA® AXI4-stream or Avalon®-ST interfaces, while registers are accessible via an AXI4-Lite, or AHB or Avalon-MM slave interface. Bridges to other interface protocols can be made available upon request. The core is Ethernet MAC-independent but can be made available pre-integrated with an Altera, Xilinx, or other third-party eMAC core.

The UDPIP-1G/10G core receives and transmits UDP packet data, and forwards other traffic from the Ethernet MAC to the application and vice versa. It also receives and transmits ARP requests and responses, and responds to ICMP echo reply messages. The core generates and validates the UDP and IP checksums of outgoing and incoming packets, respectively. It can be programmed to discard or forward corrupted packets to the user application.

The core consists of the following modules:

The Ethernet Frame Decoder receives Ethernet frames from an external Ethernet MAC, detects the frame type and sends frames to the ARP or the IP packet decoder. The Ethernet Frame Transmitter provides the external Ethernet MAC interface. The transmitter also multiplexes ARP and IP transmit packets from the core subsystems.

The VLAN Receiver receives Ethernet frames from an external Ethernet MAC, and when enabled detects and compares VLAN tag & filters frames to the correct VLAN tag. The VLAN Transmitter receives Ethernet frames from the Ethernet Frame Transmitter and adds the VLAN Tag to the frames when enabled. 

The Packet Receiver Module receives IP packets and handles them according to the packet type. The Packet Decoder receives IP packets and the decoded packets are stored in the Rx Packet Buffer and then passed to the user application.  The Received Packet Buffer implements separate data storage for the UDP application data and other data, and its size is configurable at synthesis time.

The Packet Transmit Module assembles UDP and ICMP packets. The UDP application data, as well as the ICMP packet data, are stored in the transmit buffer, the size of which is configurable at synthesis time.

The ARP Module sends and receives ARP packets and handles the packets according to command in the packet. The DHCP Module automatically requests and acquires an IP address from a DCHP server.

The UDP Channel Demultiplexer receives UDP packets and demultiplexes them according to a decoded UDP channel number. The UDP Channel Multiplexer receives UDP packet channels from a user application and multiplexes them to the Packet Transmitter module.

Finally, the Control and Status Registers control the core functionality and report the core status

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable RTL and FPGA netlist forms and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts, and comprehensive user documentation.

The UDPIP-1G/10G can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample ASIC pre-layout results reported from synthesis with a silicon vendor design kit under typical conditions, with all core I/Os assumed to be routed on-chip. The sample results do not represent the highest speed or smallest area for the core. Please contact CAST to get characterization data for your target configuration and technology.

UDP Channels

ASIC Technology

Eq. NAND2 gates

Fmax (MHz)

Memory (Bytes)

1

TSMC 65nm

28,926

333

16,640

1

TSMC 90nm

26,782

333

16,640

4

TSMC 65nm

36,308

333

24,832

4

TSMC 90nm

33,594

333

24,832

Table 1: UDPIP-1G/10G Sample Results for the core configured with a 32bit data-path (suitable for 1Gbps), ARP, ICMP, IGMP, Rx and Tx

UDP Channels

ASIC Technology

Eq. NAND2 gates

Fmax (MHz)

Memory (Bytes)

1

TSMC 65nm

39,181

333

33,024

1

TSMC 90nm

36,961

333

33,024

4

TSMC 65nm

48,528

333

49,408

4

TSMC 90nm

45,625

333

49,408

Table 2: UDPIP-1G/10G Sample Results for the core configured with a 64bit data-path (suitable for 10Gbps), ARP, ICMP, IGMP, Rx and Tx

The UDPIP-1G/10G can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family

UDP Channels

ALMs

Fmax (MHz)

Memory Bits

Arria-V
5AGXMB1G6F40C6

1
4

2,456
3,187

136
134

100,352
172,032

Cyclone-V
5CGXFC9E6F35C7

1
4

2,490
2,245

137
129

100,352
172,032

Stratix-V
5SEE9H40C4

1
4

2,380
3,091

219
241

100,352
172,032

Table 1: UDPIP-1G/10G Sample Results for the core configured with a 32bit data-path (suitable for 1Gbps), ARP, ICMP, IGMP, Rx and Tx

 

Family

UDP Channels

ALMs

Fmax (MHz)

Memory Bits

Arria-V
5AGXMB1G6F40C6

1
4

3,157
3,975

136
128

100,352
172,032

Cyclone-V
5CGXFC9E6F35C7

1
4

3,131
3,999

126
125

100,352
172,032

Stratix-V
5SEE9H40C4

1
4

3,060
3,900

209
207

100,352
172,032

Table 2: UDPIP-1G/10G Sample Results for the core configured with a 64bit data-path (suitable for 10Gbps), ARP, ICMP, IGMP, Rx and Tx

UDPIP-1G/10G reference designs have been evaluated in a variety of technologies. The following sample implementation figures for the core configured with a 32bit data-path (suitable for 1Gbps), are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device Configuration Slices / LUT4s Block RAMs Fmax (MHz)
ECP5
LFE5U-85FCABGA756
UDP Channels: 1
DHCP: Off
Multicast: Off
VLAN: Off
MTU: 2kB
Total Rx/Tx Buffers: 12kB
3,390 / 4,997 7 68
ECP5
LFE5U-85FCABGA381
UDP Channels: 4
DHCP: On
Multicast: On
VLAN: Off
MTU: 2kB
Total Rx/Tx Buffers: 20kB
6,115 / 9,041 11 52

The UDPIP-1G/10G can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).The following sample implementation figures are indicative of the core capabilities and their corresponding utilization metrics. The sample results do not represent the higher speed or smaller area for the core. Please contact CAST to get characterization data for your target configuration and technology.

Family/Device

UDP Channels

LUTs

BRAM Tiles

Fmax (MHz)

Ethernet Speed

Spartan 7

xc7s50-1

1
3,652
3

125.00

10/100/1000

4
4,929
5

Kintex U

xcku025-2

1
3,523
3

312.59

10/100/1000 and 10G

4
4,778
5

Kintex UP

xcku9p-1

1
3,678
3

312.50

10/100/1000 and 10G

4
4,988
5

Table 1:Sample Results for the core configured with a 32bit data-path, ARP, ICMP, IGMP, Rx and Tx, and without DHCP and VLAN support

 

Family/Device

UDP Channels

LUTs

BRAM Tiles

Fmax (MHz)

Ethernet Speed

Spartan 7

xc7s50-2

1
5,095
6

156,25

10/100/1000 and 10G

4
6,416
10

Kintex U

xcku025-1

1
4,999
6
4
6,299
10

Kintex UP

xcku9p-1

1
4,957
6.5
4
6,258
10

Table 2: Sample Results for the core configured with a 64bit data-path, ARP, ICMP, IGMP, Rx and Tx. and without DHCP and VLAN support

Related Content

Features List

Complete UDP/IP Hardware Stack

  • 10/100/1000 and 10G Ethernet 
  • IPv4 support without packet fragmentation
  • Jumbo and Super Jumbo Frames
  • Transmit and Receive 
  • ARP with Cache
  • ICMP (Ping Reply)
  • IGMPv3 (Multicast)
  • UDP/IP Unicast and Multicast 
  • UDP Port Filtering
  • UDP/IP Checksums generation and validation, and optional Ethernet CRC validation
  • VLAN (IEEE 802.1Q) support
  • 1 to 32 UDP transmit. and 1 to 32 UDP receive channels 
  • Ethernet Framing processing for non-UDP user-provided packets
  • Optional DHCP client

Trouble-Free Operation

  • Run time programmable network parameters
    • Local MAC address, Local IP address, Gateway IP address, and IP subnet mask
    • Per channel: Destination IP address, Source and Destination and filtered UDP ports, multicast enable/disable and receive group
  • ARP support for operation in networks with Dynamic IP allocation

Easy SoC Integration

  • 32- or 64-bit streaming capable using Avalon-ST or AXI4-Stream
  • Control/Status interface with optional 32-bit AHB, AXI, Avalon-MM or Wishbone SoC buses
  • Separate clock domains for packet processing and control/status interfaces
  • Configurable buffer sizes
  • Rich interrupt support for system events
  • Optionally available pre-integrated with:
    • Intel, Xilinx, or other third-party 1G and 10G eMAC cores
    • CAST Image and Video compression cores

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