PCI-HB
32-bit/33MHz PCI Host Bridge

This PCI Host Bridge IP core enables data transfers between a host processor and PCI bus based devices. 

The bridge allows the host to initiate PCI accesses or to respond to transactions initiated by other PCI devices.

The core complies with the PCI bus specification versions 3.0 and 2.3, and can act as a PCI master and target. Furthermore, it implements PCI bus arbitration, supporting up to seven PCI bus agents, PCI reset signal generation, and all types of PCI transactions provisioned by the standard. 

The PCI-HB builds on more than 15 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.

The core has been verified through extensive simulation, rigorous code coverage measurements and it has been proven in FPGA and ASIC designs.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:

  • HDL RTL source code 
  • Sophisticated HDL Testbench
  • Simulation script, vectors, expected results, and com-parison utility
  • Synthesis script
  • Comprehensive user documentation, including detailed specifications and a system integration guide

 
 

The PCI-HB-AHB can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample Lattice results for a single base address register configuration & support for 8 bus masters. Please contact CAST to get characterization data for your target configuration and technology.

Lattice Devices LUT4s Registers Slices SysMEM
EBRs
External I/Os Speed
(fmax, MHz)
LFSC3GA25E-6 1569 649 1187 - 65 33
LFE2-50E-6 1357 590 1029 - 65 33
LFEC6E-4 1417 594 1061 - 65 33
LFXP6C-4 1417 594 1061 - 65 33
LCMXO280C-4 1177 590 790 - 65 33

The PCI-HB-AHB can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample implementation results assuming that only the PCI I/Os are routed off-chip, and the core is configured with slices having a single base address register. Please contact CAST to get characterization data for your target configuration and technology.

Family Device LUTs BRAM DSP Fmax
(MHz)
Artix-7 7a100t-2 960 0 0 33
Kintex-7 7k160t-2 961 0 0 33

Features List

PCI Host Bridge

  • Enables data communication between the Host Processor and devices on the PCI bus
  • PCI I/O space and memory space are mapped directly to the host-bus memory space
  • PCI Interrupt and System Errors are propagated as interrupts to the host
  • PCI Configuration registers are accessible from both PCI and host directions
  • Asynchronous host and PCI clocks

PCI Interface 

  • PCI specification 3.0 and 2.3 compliant
    • 33 MHz 
    • 32-bit bus width
    • 32-bit address space
    • Parity generation and parity error detection
  • PCI Master & Target support all types of transactions:
    • Configuration space read/write
    • Memory space read/write
    • I/O Space read/write
    • Interrupt acknowledge (optional)
    • Special cycles (optional)
  • PCI reset generator
  • PCI bus arbiter 
    • Up to 7 external bus agents
    • Flexible priority schemes
    • Agent malfunction detection and reporting

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