HSDLC
HDLC & SDLC Protocol Controller

The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is based on the Intel 8XC152 Global Serial Channel (GSC) working in SDLC mode, and adds features to support HDLC or proprietary frame transmission under host processor control. 

The core operates as a peripheral to a host processor, and is easy to integrate with both modern and legacy processors. Control and status registers are accessible via an APB or a generic 80C51-like bus interface, and a comprehensive set of interrupt signals facilitates interrupt-based operation.   

The controller’s great flexibility enables a variety of serial link setups. It provides two independent interfaces, one for transmitting and one for receiving data. Both interfaces provide control signals for the link drivers to support both full- and half-duplex operation. The controller can be programmed to use hardware flow control signals (RTS/CTS) and it can also detect collisions. The baud rate is programmable and limited only by the link drivers and the core’s clock frequency. The core derives the receive clock from the received serial data, or uses an externally provided receive clock.  

The HSDLC controller core is designed for reuse and is rigorously verified and scan-ready. Although designed to manage serial links, the core contains no latches or tri-states, and is fully synchronous with a single clock domain. The core is available in Verilog RTL or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation. 

The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in several shipping customer products, and is proven in both ASIC and FPGA technologies.  

Support 

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. 

Deliverables 

The core is available in synthesizable RTL and FPGA netlist forms, and includes everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation. 

HSDLC core reference designs have been evaluated in a variety of technologies. The following are sample results, for the core configured with Tx and Rx FIFOs. FIFOs are 3 bytes each and implemented with flip-flops. Please contact CAST to get characterization data for your target configuration and technology.

ASIC Technology

Area
(eq. NAND2 gates)

Max. Freq.
(MHz)

TSMC 65nm LP 7,575 400
TSMC 40nm G 5,594 1,200
TSMC 28nm HPM 4.588 1,800

The HSDLC can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Supported Family /
Devices
Logic Memory
Bits
Frequency
(MHz)

Cyclone-V
5CEBA9F31C7

412 ALMs 0 162

Arria-V

5AGXBB3D4F35C4
414 ALMs 0 202

Arria10

10AS057K2F35I2LG
420 ALMs 0 327

Max10

10M50DAF484C6GES
836 LEs 0 136

The HSDLC can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample performance and resource utilization data. Please contact CAST to get characterization data for your target configuration and technology.

Supported Family LUTs RAMBs/DPSs Performance
(MHz)

Artix-7

XC7A200T-3
588 0/0 242

Kintex-7

XC7K420T-3
607 0/0 356

Kintex Ultrascale

XCKU085-3
597 0/0 448

Features List

  • Controller for both the SDLC and HDLC (ISO 13239) transmission protocols
    • Based on the Intel 8XC152 Global Serial Channel (GSC), operating in SDLC Mode
    • Additional features support HDLC and proprietary serial protocols.
  • Flexible Frame Formatting
    • Programmable preamble pattern and preamble length
    • Programmable inter-frame space
    • Single- or double-byte address field
    • Address filtering allowing multicast and broadcast
    • Raw transmit and receive testing modes
    • Back-to-back transmit & back-to-back receive
    • NRZ, NRZI, Bi-Phase-S, and Manchester Data Encoding
    • Bit Stuffing and Bit Stripping
    • 16-bit (CRC-16, CCITT or IBM) and 32-bit (CRC-32) frame check sequence
    • CRC, Bit-stuffing/stripping, and abort and idle sequences detection can be independently enabled/disabled
    • Receiver FIFO Packet counter
  • Flexible Serial Link Interface
    • Full or Half Duplex
    • Programmable Baud Rate
    • Modem Controls (RTSn/CTSn)
    • Collision detection
    • Internal baud generator, or external transmit clock with strobe
    • Automatic receive clock recovery, or external receive clock with strobe
  • Easy to Integrate
    • Suitable for interrupt-based or polling-based operation
    • Configurable size, Transmit & Receive FIFOs
    • 80XC152-like control status registers
    • APB or Generic MCU-like Host Interface

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