|
It’s the season for Halloween or similar day of the dead celebrations around the world, but at CAST we’re less scared about the IP market than ever.
We proudly continue to add high-quality products, whether leading-edge — like the CANsec core described below — or more conventional — like our own TCP/IP Stack, also described below. We are growing at a significant pace — see the note below on job openings — and we recently held a company-funded three-day reunion in Crete. Nearly fifty staff members, partners, former employees, spouses, and friends of the company gathered there from around the world for training and team building (see this post).
If the season has you scared about fiendishly tight project timelines or frightening technical challenges, give us a call or email to see how CAST IP might help.
-- Nikos, Zervas, CEO, [email protected], +1 201.391.830
|
|
Introducing the First CANsec IP Core
|
|
|
|
 We recently announced what we believe is the first shipping hardware acceleration engine for the CANsec security standard. It works with any CAN XL bus controller and uses NIST-approved AES ciphers to protect data integrity, authenticity, and confidentiality on the CAN XL bus.
The new CAN-SEC CANsec Acceleration Engine IP core adds this layer of security in conformance with the CAN in Automation (CiA) draft specification 613-1 and -2. We source this from partner Fraunhofer IPMS, and it is available now.
“As with CAN in 2002, TSN Ethernet in 2017, and CAN XL in 2020, the advanced research and development team at Fraunhofer IPMS has enabled us to provide one of the first available IP cores for a hugely-beneficial new technology.”
Nikos Zervas, CAST CEO
Read more in the press release. ►
|
|
The First in a Series of CAST TCP/IP Hardware Stacks is Shipping Now
|
|
|
 We recently announced a 1G/10G TCP/IP hardware stack IP core that offers benefits beyond similar “offload engines.”
The new TCPIP-1G/10G can implement the entire stack in hardware: IP, VLAN, ARP, ICMP (ping), DHCP client, UDP stack, and TCP. It runs without assistance from a system processor, is highly efficient in power and silicon usage, and has many configurable options, such as handling from 1 to over 32,000 simultaneous channels. It’s also portable: customers can order RTL for ASICs or an optimized netlist for devices from nearly any FPGA provider.
“We’ve worked with networking IP users for years and learned from the TCP/IP stacks already available to engineer what we believe is a better core that can satisfy the requirements of nearly any system needing TCP/IP communication.”
Andreas Emeretlis, hardware design engineer for CAST
The TCPIP-1G/10G Hardware Stack is shipping now. We plan to offer faster, 40G and 100G capable cores next year. Learn more in the press release. ► |
|
Built-In Floating Point Unit Expands RISC-V Processor Applications
|
|
|
 The RISC-V BA51 is a royalty-free, low-power, embedded processor that’s an excellent solution for applications like mixed-signal processing, wireless communications management, or industrial microcontrollers.
Sourced from Beyond Semiconductor, we first introduced it in 2021. Now it’s also suitable for more advanced applications with a new option for an integrated floating point unit (FPU). This FPU gives the BA51 support for RISC-V ISA extensions F for floating point operations and D for double-precision operations, letting the processor perform more complex functions.
The BA51 with optional FPU is shipping now and is already in use by a major customer. You can learn more on the BA51 product page.► |
|
TSN Ethernet Capabilities Continue to Grow
|
|
|
 Being one of the first to market with Time Sensitive Networking Ethernet cores isn’t enough for our partner Fraunhofer IPMS, who continues to add capabilities to the TSN Endpoint, Switch, and Switched Endpoint cores we offer.
Now you can optionally implement hardware Frame Replication and Elimination for Reliability (FRER, IEEE 802.1CB) for applications requiring zero data packet losses. You can also prevent network traffic overloads with built-in Per-Stream Filtering and Policing (PDFP, IEEE 802.1Qci).
Also new is support for these two features in software: Path Control and Reservation (PCR, IEEE 802.1Qca) configures multiple paths in bridged networks, and Stream Reservation Protocol (SRP) Enhancements and Performance Improvements (IEEE 802.1Qcc-2018) reduces delays from multiple SRP requests for the most critical network traffic.
If you’re considering moving to TSN Ethernet for automotive, industrial, or other applications, give us a call (+1 800.391.8300) or email to discuss your needs. Our engineering and sales teams are likely to have more TSN IP core experience than anyone else you might find.
|
|
 Consider joining one of the most successful still-independent digital IP companies. We’re looking for engineering, marketing, and sales candidates who share our attention to technical excellence, focus on easy IP reuse, and commitment to fantastic customer service and satisfaction.
Check out the current openings on our Careers page. ► |
|
Upcoming Events
D&R IP-SoC Conference '22
Nov. 30, 2022 – Dec. 1, 2022
Grenoble, France
Paper: Addressing Performance Challenges of TCP/IP Stack Implementations
Embedded World 2022
June 21, 2022 – June 23, 2022
Exhibition Centre, Nuremberg, Germany
Booth:4-561
59th DAC
July 11, 2022 – July 13, 2022
Moscone West Center, San Francisco
Booth 1506 |
|
|
|
|
