CAN-CTRL
CAN 2.0 & CAN FD Bus Controller

Implements a CAN bus controller that performs serial communication according to CAN 2.0 and CAN FD specifications. It supports the original Bosch protocol and ISO specifications as defined in ISO 1989—including time-triggered operation (TTCAN) as specified in ISO 19898-4—and is also optimized to support the popular AUTOSAR and SAE J1939 specifications. 

The CAN protocol uses a multi-master bus configuration for the transfer of frames between nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between various components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames.

The CAN-CTRL core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It implements a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application. 

The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable. The transmit buffer can operate in FIFO or priority mode. 

The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance, and optimization features. 

The CAN-CTRL is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The deliverables for this version include a Safety Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA), and the ISO-26262 ASIL-B Ready certificate, issued by SGS-TÜV Saar GmbH. An ASIL-C compatible version can be made available and undergo certification upon request.

The core is extensively verified, proven in several plug fests and a large number of production designs.

    Verification

    The core has been rigorously verified and has been production proven multiple times.
    It has been verified through extensive synthesis, place and route, simulation runs, Verification IP, and PlugFests. It has been embedded in several shipping customer products, and is proven in both ASIC and FPGA technologies.
     

    Support

    The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

    Deliverables

    The core includes everything required for successful implementation:

    • VHDL or Verilog RTL source code
    • Post-synthesis netlist 
    • Testbenches
      • Behavioral tests
      • Post-synthesis verification
    • Simulation scripts
    • Synthesis scripts
    • Linux driver
    • Documentation
    • The optional safety-enhanced package includes the Safe-ty Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA) and the ASIL-B Ready certificate, issued by SGS-TÜV Saar GmbH.

    The CAN-CTRL can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available).  The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping). Please contact CAST to get characterization data for your target configuration and technology.

    Technology CAN 2.0 CAN-FD
    Cell Area Memory Bits Cell Area Memory Bits
    TSMC 65nm LP

    14,700 um2
    11,500 eq. Gates

    1,088

    18,000 um2
    14,000 eq. Gates

    4,224

    TSMC 40nm G

    7,350 um2
    10,800 eq. Gates

    8,800 um2
    12,900 eq. Gates

    TSMC 28nm HPC

    4,380 um2
    8,700 eq. Gates

    5,260 um2
    10.441 eq. Gates

     

    The CAN-CTRL can be mapped to any Intel FPGA device (provided sufficient silicon resources are available). The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping). Please contact CAST to get characterization data for your target configuration and technology.

    Family Device CAN 2.0 CAN-FD
    Logic Memory Logic Memory

    Max 10
    10M50

    2,343 LEs
    0 MULTs

    1,088 bits
    3 RAM Blocks

    2,806 LEs
    0 MULTs

    4,224 bits
    3 RAM Blocks

    Cyclone V
    5CEFA7

    1,094 ALMs
    1 DSP

    1,325 ALMs
    1 DSP

    Cyclone 10 LP
    10CL120

    2,331 LEs
    0 MULTs

    2,808 LEs
    0 MULTs

    Cyclone 10 GX
    10AX115

    1,072 ALMs
    1 DSP

    1,317 ALMs
    1 DSP

    Arria V GX
    5AGXBB3

    1,092 ALMs
    1 DSP

    1,217 ALMs
    1 DSP

    Arria 10 GX
    10AX115

    1,117 ALMs
    1 DSP

    1,333 ALMs
    1 DSP

     

    Note: Host and CAN clock constrained to 80MHz

    The CAN-CTRL can be mapped to any Lattice Device (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements.. The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include TTCAN).

    Family & Device

    CAN-FD Support

    Logic Block RAMs Host Clock (MHz) CAN Clock (MHz)

    ICE
    40U/P5k

    Yes

    3,883 LCs
    544 PLBs

    6

    42

    25

    ICE
    40U/P5k

    No

    2,932 LCs
    452 PLBs

    6

    45

    25

    MachXO2
    7000HC

    Yes

    1,530 Slices
    3,025 LUT4s

    4

    59

    23

    MachXO2
    7000HC

    No

    1,248 Slices
    2,466 LUT4s

    0

    62

    29

    CAN-CTRL reference designs have been evaluated in a variety of technologies. The following are sample results optimized for area with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN or CAN FD).


    Family
    Utilization (Cells or Tiles)

    RAM
    Blocks

    Frequency
    (MHz)
    Sequential Combinatorial
    ProASIC3
    A3P1000-2

    990

    3,940

    6

    20

    SmartFusion2 
    M2S150-STD

    2,595  4LUT

    1,089 DFF

    -

    20

    Igloo2 
    M2GL150-STD

    2,595 4LUT

    1,089

    -

    20

     

    The CAN-CTRL can be mapped to any Xilinx FPGA device (provided sufficient silicon resources are available).  The following are sample results for the core configured with three receive buffers, three transmit buffers, and three acceptance filters (does not include priority mode, TTCAN and CiA603 timestamping). Please contact CAST to get characterization data for your target configuration and technology.

    Family Device CAN 2.0 CAN-FD
    Logic Memory Logic Memory

    Artix-7
    XC7A15T

    1,616 LUTs
    511 Slices

    1,088 bits
    1 RAMB36

    1,952 LUTs
    652 Slices

    4,224 bits
    1 RAMB36

    Virtex-7
    XCVX300T

    1,612 LUTs
    522 Slices

    1,942 LUs
    646 Slices

    Kintex UltraScale
    XCKU060

    1,595 LUTs
    240 CLBs

    1,937 LUTs
    296 CLBs

    Kintex UltraScale+
    XKU15P

    1590 LUTs
    264 CLBs

    1,941 LUTs
    337 CLBs


    Note: Host and CAN clock constrained to 80MHz

    Related Content

    Features List

    CAN Specifications Support

    • CAN 2.0 & CAN-FD (ISO 11898-1.2015, plus earlier ISO and Bosch specifications) 
    • TTCAN (ISO 11898-4 level 1) 
    • Optimized for AUTOSAR and SAE J1939

    Enhanced Functionality

    • Error Analysis features enabling diagnostics, system maintenance, and system optimization:
      • Last error type
      • Arbitration lost position
      • Error Warning Limit
    • Listen-Only Mode enables CAN bus traffic analysis and automatic bit-rate detection
    • Loop back mode for self-testing
    • Time-stamping support, compliant to CiA's 603 specification

    Flexible Message Buffering and Filtering

    • Configurable number of:
      • Receive buffers
      • Lower-priority transmit buffers
      • Independently programmable acceptance filters, 1 to 16
    • One high-priority transmit buffer
    • FIFO or priority mode for transmit buffers

    Easy to Use and Integrate

    • Programmable data rate up to 1 Mbit/s with CAN 2.0 and several Mbit/s with CAN FD option
    • Programmable baud rate prescaler: 1 up to 1/256
    • Single Shot Transmission Mode for lower software overhead and fast reloading of transmit buffer
    • Programmable interrupt sources
    • Generic 8-bit host-controller interface and optional 32-bit AMBA-APB or 32-bit AHB-Lite
    • A single host can control multiple CAN bus nodes via an optional Multi-CAN wrapper

    Safety Enhanced Version (optional)

    • ISO-26262 ASIL-B Ready
      • Implements ECC for SRAM and spatial redundancy for inner logic protection
    • ISO-26262 ASIL-C on request

    Zero Risk

    • Compatible with any CAN2.0 transceiver (PHY) that supports ISO-11898, and various CAN-FD PHYs from NXP, MicroChip, OnSemi, Infineon, etc.
    • Multiple times production proven

    Efficient and Portable Design

    • Available in RTL, and portable to ASIC and FPGA technologies

    Verification IP

    Available for this core: CAN-VIP

    Let's talk about your project and our IP solutions

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