R8051XC2

High-Performance, Configurable, 8-bit Microcontroller

The core’s architecture eliminates redundant bus states and implements parallel processing of fetch and execution phases. Since a cycle is aligned with memory fetch when possible, most of the 1-byte instructions are performed in a single cycle. 

The core uses one clock per cycle. This, together with other extensions (multi-DPTR, MDU), leads to significant performance improvements with respect to the original Intel device operating with the same clock frequency.

The Dhrystone 2.1 benchmark score varies from 0.088 to 0.114 DMIPS/MHz, which translates to speed improvements from 9.4 to 12.1 times over the standard 80C51, or 1200 times the maximum performance at 1.2 GHz in 40nm technology.

Sample Dhrystone 2.1 benchmark results are as follows.

Three versions of the core are available, offering a range of capabilities and prices.

• R8051XC2-A includes options that match the original Intel 8051 peripheral set: 64kB memory interface, two timers, one serial port, four parallel I/O Ports, two-level interrupt controller, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
• R8051XC2-B includes options that match the Infineon 80515/80517 peripheral set: 64kB memory interface, three timers, two serial ports, four parallel I/O ports, watchdog timer, multiplication-division unit, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).
• R8051XC2-F includes the full set of options, and is user-configurable (i.e., options may be included or excluded prior to synthesis). 

ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.
The native debugging package is an extra option for all versions.

The core has been verified through extensive synthesis, place and route, and simulation runs. It has been embedded in numerous shipping customer products, and is proven in both ASIC and FPGA technologies.

The core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation. ASIC versions include:

• HDL RTL source code 
• Easy-to-use configuration tool (with configurable versions)
• An example chip implementation, which uses the core in a sample system
• Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
• Simulation script, vectors, and expected results
• Synthesis script
• Comprehensive user documentation, including detailed specifications and a system integration guide
• A reference design board is available; contact CAST Sales for information 

The R8051XC2 can be mapped to any ASIC technology or FPGA device (provided sufficient silicon resources are available). The following table provides sample results using a 90nm ASIC technology, and separate optimizations for speed and area. The EASE debug option is not included. Please contact CAST to get characterization data for your target configuration and technology.Reference designs have been evaluated in a variety of technologies.